ISP1505ABSUM STEricsson, ISP1505ABSUM Datasheet - Page 29

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ISP1505ABSUM

Manufacturer Part Number
ISP1505ABSUM
Description
Manufacturer
STEricsson
Datasheet

Specifications of ISP1505ABSUM

Number Of Transceivers
1
Esd Protection
YeskV
Operating Supply Voltage (typ)
Not RequiredV
Operating Temperature Classification
Industrial
Operating Supply Voltage (max)
Not RequiredV
Operating Supply Voltage (min)
Not RequiredV
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Lead Free Status / RoHS Status
Compliant

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NXP Semiconductors
ISP1505A_ISP1505C_3
Product data sheet
For more information, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 .
b. Host chirp: If the host does not detect the peripheral chirp, it must continue
c. High-speed idle: The peripheral must detect a minimum of Chirp K-J-K-J-K-J. Each
than 7 ms after reset time T
up its clock within 5.6 ms, leaving 200 s for the link to start transmitting the
Chirp K, and 1.2 ms for the Chirp K to complete (worst case with 10 % slow clock).
asserting SE0 until the end of reset. If the host detects the peripheral Chirp K for
no less than 2.5 s, then no more than 100 s after the bus leaves the Chirp K
state, the host sends a TXCMD (NOPID) with an alternating sequence of Chirp Ks
and Js. Each Chirp K or Chirp J must last for no less than 40 s and no longer than
60 s.
Chirp K and Chirp J must be detected for at least 2.5 s. After seeing that
minimum sequence, the peripheral sets TERMSELECT = 0b and
OPMODE[1:0] = 00b. The peripheral is now in high-speed mode and sees !squelch
(01b on LINESTATE). When the peripheral sees squelch (10b on LINESTATE), it
knows that the host has completed chirp and waits for Hi-Speed USB traffic to
begin. After transmitting the chirp sequence, the host changes OPMODE[1:0] to
00b and begins sending USB packets.
Rev. 03 — 26 August 2008
0
. If the peripheral is in low-power mode, it must wake
ULPI HS USB host and peripheral transceiver
ISP1505A; ISP1505C
© NXP B.V. 2008. All rights reserved.
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