TMC22053KHC Fairchild Semiconductor, TMC22053KHC Datasheet - Page 27

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TMC22053KHC

Manufacturer Part Number
TMC22053KHC
Description
Manufacturer
Fairchild Semiconductor
Datasheet

Specifications of TMC22053KHC

Screening Level
Commercial
Package Type
MQFP
Pin Count
100
Lead Free Status / RoHS Status
Compliant
PRODUCT SPECIFICATION
Control Register Definitions
Buffered register set 0 (1C)
Buffered register set 0 (1D)
Buffered register set 0 (1E)
Buffered register set 0 (1F)
Normalized Subcarrier Frequency (20)
Reg
1C
Reg
1D
1D
1D
Reg
1E
1E
Reg
1F
Reg
20
20
SYSPH0
SYSPH0
YOFF0
FSC
7
7
7
7
7
3
7
Bit
7-3
2
1-0
Bit
7-1
0
15
Bit
7-0
Bit
7-4
3-0
Bit
7-0
7
SYSPH0
SYSPH0
YOFF0
Name
Reserved
YOFF0
SG0
Name
SYSPH0
VAXIS
Name
SYSPH0
Name
FSC
Reserved
Name
YOFF0
FSC
6
6
6
6
6
2
1-0
3-0
6
14
6
0
8
7-0
7-1
15-8
SYSPH0
SYSPH0
Reserved
YOFF0
Active when BUFFER pin set LOW.
Active when BUFFER pin set LOW.
Active when BUFFER pin set LOW.
Active when BUFFER pin set LOW.
FSC
5
5
5
5
5
1
Description
Y offset, 8 lsbs. Bottom 8 bits of luma or RGB offset
Description
Reserved, set to zero.
Y offset, msb. msb of YOFF
Msync gain, 2 msbs. Top 2 bits of mixed sync scalar.
msb = 2
Description
7 lsbs of phase. Bottom 7 bits of the system phase offset
V axis Flip. The PAL V axis sign bit is flipped when HIGH.
Description
8 msbs of phase offset. Top 8 bits of 15 bit phase offset.
Description
Bottom 4 bits of fsc. Bottom 4 bits of the 28 bit subcarrier SEED
Reserved, set to zero.
5
13
5
(continued)
SYSPH0
SYSPH0
YOFF0
FSC
4
4
4
4
4
0
4
12
4
SYSPH0
SYSPH0
YOFF0
3
3
3
3
3
3
11
3
SYSPH0
SYSPH0
YOFF0
YOFF0
2
2
2
2
2
2
8
10
Reserved
2
SYSPH0
SYSPH0
YOFF0
SG0
1
1
1
1
1
1
1
1
9
SYSPH0
YOFF0
VAXIS
SG0
TMC22x5y
0
0
0
0
0
0
0
0
8
27

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