TMC22152KHC Fairchild Semiconductor, TMC22152KHC Datasheet - Page 52

• Manufacturer Part Number: TMC22152KHC
• Manufacturer: Fairchild Semiconductor

Specifications of TMC22152KHC

• Screening Level: Commercial
• Package Type: MQFP
• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

TMC22x5y
.
Digital Burst Locked Loop
The digital burst locked loop provides sine and cosine signals
which are phase locked to the incoming burst signal. These
sine and cosine signals are used to demodulate the chromi-
nance data, producing the U and V color-difference signals.
The U data are phase-referenced to sin(wt) and the V data to
cos(wt). The demodulated signal is passed through a low pass
filter to remove signals at twice the subcarrier frequency.
The magnitude of the U and V data within the demodulated
burst signal provides the error signal which, after filtering, is
used to adjust the frequency and/or phase of the subcarrier
DDS. The output of the subcarrier DDS is translated into sine
and cosine signals in ROM-based lookup tables.
The PALODD signal is low on lines without the 180 degree
phase advance in the modulated V signal, termed NTSC
lines, and high for lines with the 180 degree phase advance,
termed PAL lines. This signal is used in the burst locked loop
to advance the phase of the cosine table on PAL lines. PAL-
ODD is always low for NTSC.
Color Kill Counter
The demodulated U and V components are compared to a
programmable burst level threshold. If both the U and V data
fall below this threshold, a color kill flag is set high. The
color kill counter is incremented once per line if the color
kill flag is high. If the count reaches 127 within one field, the
color kill circuit becomes active during the next field group.
When this occurs, the input video will be passed unaltered
on the luminance channel and the color difference signals
will be set to chroma black.
The color kill signal remains active until a field with less
than 127 lines without burst is encountered, at which time,
during the next vertical blanking period, the decoder is reset.
The operation of the color kill logic can be monitored exter-
nally by reading the MONO register bit in register 44h. The
MONO bit is HIGH for composite and YC video signals and
LOW for monochrome signals.
Field Flag, FLD
The FLD signal is the lsb of the field count FID
LOW for fields where the first vertical sync occurs in the first
half of the line and is HIGH for fields when it occurs in the
second half of the line. This signal is synchronized with the
frame and color frame flags in the FID generator.
52
Chrominance
Figure 21. Block Diagram of Digital Burst Locked Loop
Locked Loop
–
Burst
2-0
cos(wt+f)
and is
sin(wt)
Frame Bit
NTSC
The middle bit (frame bit) of the field count is determined,
by the phase of the subcarrier on a given pixel and on a given
line. The signal used to determine this is NFDET (New Field
DETect), and occurs when the line count is zero and the pixel
count is one of four programmable pixel positions, zero, one,
two, or three.
PAL
The frame bit in PAL is detected through the Bruch blanking
sequence. The error signal control circuit generates a color
kill flag whenever a line is detected without a burst. It is
therefore possible to compare this signal with specific line
idents to determine the field sequence in both PAL-I and
PAL-M. A set of specific patterns determine the correct
phase of FID
is forced to a known state and then flywheels until the next
fixed pattern is detected.
Table 9. PAL-B,G,H,I Bruch Blanking Sequence
The frame bit is low for frames 0 and 2 and high for frames 1
and 3.
Internal
line #
309
309
309
309
5
6
5
6
Gaussian
Gaussian
LPF
LPF
1
; if any of these patterns is detected then FID
present
Burst
Yes
Yes
Yes
Yes
No
No
No
No
U Data
V Data
Internal
frame #
0 or 2
0 or 2
0 or 2
0 or 2
1 or 3
1 or 3
1 or 3
1 or 3
65-22x5y-62
PRODUCT SPECIFICATION
Internal field #
0 or 4
0 or 4
1 or 5
1 or 5
2 or 6
2 or 6
3 or 7
3 or 7
1