TMC22152KHC Fairchild Semiconductor, TMC22152KHC Datasheet - Page 58

• Manufacturer Part Number: TMC22152KHC
• Manufacturer: Fairchild Semiconductor

Specifications of TMC22152KHC

• Screening Level: Commercial
• Package Type: MQFP
• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

TMC22x5y
Sync Pulse Generator
The vertical and horizontal references to the decoder can be
from external VSYNC and HSYNC pulses, decoded from
TRS and TRS-ID words, or from the internal sync separator
which extracts the sync information from the digitized input
video.
The sync pulse generator (SPG) provides all the clock and
enable pulses required to synchronize the decoder operation
to the incoming video signal. These pulses are described
below, along with the microprocessor data required to
control them.
Internal Field and Line Numbering Scheme
The internal line numbering of the digital decoder differs
from the standard video line numbering as shown in the
following tables. The internal line numbers for a 3 line comb
advance the numbering by 1 line with respect to the input,
but are identical with respect to the internally one line
delayed decoded video.
Table 15. NTSC Field and Line Numbering
Table 16. PAL B,G,H,I Field and Line Numbering
Table 17. PAL M Field and Line Numbering
HSTBG (Burst gate)
The burst gate starts the 16 clock period average of the
demodulated burst envelope. The position of the burst gate is
programmed into a register as the number of clock periods
from the falling edge of sync to the burst envelope.
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Standard
Standard
Standard
Signal is available over the microprocessor data bus.
Field #
Field #
Field #
1 & 3
1 & 3
2 & 4
2 & 4
1 & 5
2 & 6
3 & 7
4 & 8
1 & 5
2 & 6
3 & 7
4 & 8
938 - 1250
Standard
264 - 265
266 - 525
Standard
313 - 625
626 - 937
Standard
263 - 525
263 - 525
4 - 263
1 - 312
Line #
Line #
1 - 262
1 - 262
Line #
1 - 3
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Internal
Internal
Internal
Field #
Field #
Field #
1 & 3
0 & 2
0 & 2
1 & 3
0 & 4
1 & 5
2 & 6
3 & 7
0 & 2
1 & 3
0 & 2
1 & 3
Internal Line
Internal Line
Internal Line
260 - 262
260 - 261
0 - 311
0 - 312
0 - 311
0 - 312
0 - 261
0 - 262
0 - 261
0 - 262
0 - 259
0 - 259
#
#
#
HBLK (Horizontal Blanking Period)
The horizontal blanking period is LOW between the start of
SAV and the end of EAV. This signal is used in several
places:
a) To clear the SYSPH offset when LOW, this is required
b) To aid in the comb filter management,
c) To remove the burst envelope on the demodulated UV
d) To remove the syncs on the BLUE and RED outputs.
BBLK (Vertical Burst Blanking Period)
The vertical burst blanking blanks the lines with no burst
from the burst phase locked loop. This signal is decoded from
the line ident, LID
and the field count.
MBLK (Mixed Blanking)
This signal is used in the matrix to switch between the
sync scalar and the luma scalar. The MBLK signal is active
whenever HBLK is active or becomes active when VBLK
becomes active. MBLK is also active in PAL on line 310
when both VACT1 and FLD are HIGH and in NTSC and
PAL M on line 259 when VACT2 is HIGH and FLD is LOW.
FLD
The FLD is LOW for field 1 and HIGH for field 2.
LID
The line ID signals are used in the vertical comb filter
management to control the comb filter on the leading and
trailing lines of active video around the vertical blanking
period, to start and stop the VINDO operation, and in gener-
ating the vertical blanking and burst blanking periods.
VACT2
VACT2 is HIGH during the second half of all active lines.
GRABF
The GRABF signal goes HIGH when the internal field count
is equal to the programmed field number for the GRAB
operation. f a pixel grab is being, this signal is held HIGH to
not inhibit the GRABS signal on each line.
GRABL
The GRABL signal goes HIGH when the internal line count
is equal to the programmed line number for the GRAB
operation. If a pixel grab is being performed, this signal is
held HIGH to not inhibit the GRABS signal on each line.
GRABP
The GRABP signal goes HIGH when the internal pixel count
is equal to the programmed pixel number for the GRAB
operation.
DVSYNC and DHSYNC (Output Pins)
The DVSYNC and DHSYNC signals are active when GCR
is LOW. When GCR
Three line comb based decoders have an inherent line delay,
therefore the input VSYNC and HSYNC signals can not be
just delayed by a few registers and output as DVSYNC and
DHSYNC: they need to be delayed by one complete line. In
all other comb filter configurations the DVSYNC and
4-0
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for correct operation of the subcarrier phase locked loop,
data,
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4-0
2
, and is modified by the video standard
is HIGH these signals are three stated.
PRODUCT SPECIFICATION
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2