SAF7118HV1 NXP Semiconductors, SAF7118HV1 Datasheet - Page 36

• Manufacturer Part Number: SAF7118HV1
• Manufacturer: NXP Semiconductors

Specifications of SAF7118HV1

• Screening Level: Industrial
• Package Type: PQFP
• Pin Count: 160
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SAF7118_4
Product data sheet
8.2.1 RGB-to-(Y-C
8.2.2 Downformatter
The matrix converts the RGB signals from the analog-to-digital converters/downsamplers
to the Y-C
has a gain factor of 1. The block provides a delay compensated bypass for component
input signals.
The matrix is represented by the following equations:
The block mainly consists of 2 parts: the color difference signal downsampler and the
Y-path.
The color difference signals are first passed through low-pass filters which reduce alias
effects due to the lower data rate. The ITU sampling scheme requires that both color
difference samples fit to the first Y sample of the current time slot. Thus the C
delayed by 1 clock before it is fed to the multiplexer. The switch signal defines the data
multiplex phase at the output: a ‘0’ marks the first clock of a time slot, this is a C
The output is fed through a register, so that the multiplexer runs with the opposite phase.
The delay compensation for the Y signal already provides most of the registers required
for a small high-pass filter. It can be used to compensate high frequency losses in the
analog part. It provides 2 dB gain at 6.75 MHz.
The Y high-pass filter frequency response is shown in
is 1, so a limiter is required at the filter output. The current implementation clips at the
maximum values of 0 and 511. The entire filter can be controlled by the I
in subaddress 29h.
Fig 26. Downformatter block diagram
•
•
•
Y = 0.299
C
C
B
R
= 0.5772
= 0.7296
B
-C
R
switch
CMFI
B
representation. The input and output word widths are 9 bits. The matrix
C
C
-C
R + 0.587
Y
R
B
R
(B
(R
) matrix
HIGH-PASS
LOW-PASS
Y)
Y)
LOW-PASS
Rev. 04 — 4 July 2008
bypass
G + 0.114
Multistandard video decoder with adaptive comb filter
D
Q
B
delay compensation
D
n
Q
0
1
Figure
D
28. The DC gain of the filter
Q
(C
mhb732
Y
R
OUT
-C
SAF7118
© NXP B.V. 2008. All rights reserved.
B
2
)
OUT
C-bus bit CMFI
R
signal is
B
sample.
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