ADV7176AKSZ Analog Devices Inc, ADV7176AKSZ Datasheet - Page 23

• Manufacturer Part Number: ADV7176AKSZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7176AKSZ

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: MQFP
• Pin Count: 44
• Lead Free Status / RoHS Status: Compliant

REGISTER ACCESSES
The MPU can write to or read from all of the ADV7175A/
ADV7176A registers except the subaddress register, which is a
write-only register. The subaddress register determines which
register the next read or write operation accesses. All communi-
cations with the part through the bus start with an access to the
subaddress register. A read/write operation is performed from/to
the target address, which then increments to the next address
until a stop command on the bus is performed.
REGISTER PROGRAMMING
The following section describes each register, including subaddress
register, mode registers, subcarrier frequency registers, subcarrier
phase register, timing registers, closed captioning extended data
registers, closed captioning data registers and NTSC pedestal
control registers in terms of its configuration.
Subaddress Register (SR7–SR0)
The communications register is an 8-bit write-only register.
After the part has been accessed over the bus, and a read/write
operation is selected, the subaddress is set up. The subaddress
register determines to/from which register the operation takes
place.
Figure 31 shows the various operations under the control of
the subaddress register. Zero should always be written to
SR7–SR6.
Register Select (SR5–SR0)
These bits are set up to point to the required starting address.
BE WRITTEN TO
ZERO SHOULD
MR17
0
1
COLOR BAR
THIS BIT
MR07
CONTROL
(0)
DISABLE
ENABLE
MR17
MR06
0
1
MR16
0
1
OUTPUT SELECT
MR07
CONTROL
YC OUTPUT
RGB/YUV OUTPUT
NORMAL
POWER-DOWN
DAC A
MR16
MR15
MR06
0
1
MR05
CONTROL
NORMAL
POWER-DOWN
0
1
DAC B
RGB SYNC
MR15
DISABLE
ENABLE
MR14
MR05
0
1
MR04 MR03
LUMINANCE FILTER CONTROL
CONTROL
0
0
1
1
NORMAL
POWER-DOWN
DAC D
MR14
0
1
0
1
MR04
MR13
0
1
LOW PASS FILTER (A)
NOTCH FILTER
EXTENDED MODE
LOW PASS FILTER (B)
MR13
CONTROL
NORMAL
POWER-DOWN
MODE REGISTER 0 MR0 (MR07–MR00)
(Address [SR4–SR0] = 00H)
Figure 32 shows the various operations under the control of Mode
Register 0. This register can be read from as well as written to.
MR0 BIT DESCRIPTION
Output Video Standard Selection (MR01–MR00)
These bits are used to set up the encode mode. The ADV7175A/
ADV7176A can be set up to output NTSC, PAL (B, D, G, H, I)
and PAL (M) standard video.
Pedestal Control (MR02)
This bit specifies whether a pedestal is to be generated on
the NTSC composite video signal. This bit is invalid if the
ADV7175A/ADV7176A is configured in PAL mode.
Luminance Filter Control (MR04–MR03)
The luminance filters are divided into two sets (NTSC/PAL) of
four filters, low-pass A, low-pass B, notch and extended. When
PAL is selected, bits MR03 and MR04 select one of four PAL
luminance filters; likewise, when NTSC is selected, bits MR03
and MR04 select one of four NTSC luminance filters. The fil-
ters are illustrated in Figures 4 to 12.
RGB Sync (MR05)
This bit is used to set up the RGB outputs with the sync infor-
mation encoded on all RGB outputs. (This funcionality is only
available on the ADV7176A.)
Output Select (MR06)
This bit specifies if the part is in composite video or RGB/YUV
mode. Please note that the main composite signal is still avail-
able in RGB/YUV mode.
DAC C
MR03
MR12 MR11
0
0
1
1
MR02
0
1
MR12
CLOSED CAPTIONING
FIELD SELECTION
PEDESTAL
0
1
0
1
CONTROL
MR02
PEDESTAL OFF
PEDESTAL ON
NO DATA OUT
ODD FIELD ONLY
EVEN FIELD ONLY
DATA OUT
(BOTH FIELDS)
MR11
MR01 MR00
0
0
1
1
STANDARD SELECTION
MR10
MR01
0
1
INTERLACED MODE
OUTPUT VIDEO
0
1
0
1
ADV7175A/ADV7176A
INTERLACED
NONINTERLACED
MR10
CONTROL
NTSC
PAL (B, D, G, H, I)
PAL (M)
RESERVED
MR00