ADV7176AKSZ Analog Devices Inc, ADV7176AKSZ Datasheet - Page 26

• Manufacturer Part Number: ADV7176AKSZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7176AKSZ

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: MQFP
• Pin Count: 44
• Lead Free Status / RoHS Status: Compliant

ADV7175A/ADV7176A
Genlock Selection (MR22–MR21)
These bits control the genlock feature of the ADV7175A/
ADV7176A. Setting MR21 to a Logic “1” configures the
SCRESET/RTC pin as an input. Setting MR22 to Logic Level
“0” configures the SCRESET/RTC pin as a subcarrier reset
input, therefore, the subcarrier will reset to Field 0, following a
low-to-high transition on the SCRESET/RTC pin. Setting
MR22 to Logic Level “1” configures the SCRESET/RTC pin as
a real-time control input.
Active Video Line Width Control (MR23)
This bit switches between two active video line durations. A
zero selects CCIR.REC601 (720 pixels PAL/NTSC) and a one
selects ITU-R.BT.470 “analog” standard for active video dura-
tion (710 pixels NTSC 702 pixels PAL).
Chrominance Control (MR24)
This bit enables the color information to be switched on and off
the video output.
Burst Control (MR25)
This bit enables the burst information to be switched on and off
the video output.
RGB/YUV Control (MR26)
This bit enables the output from the RGB DACs to be set to
YUV output video standard. Bit MR06 of Mode Register 0
must be set to Logic Level “1” before MR26 is set.
Lower Power Mode (MR27)
This bit enables the lower power mode of the ADV7175A/
ADV7176A. This will reduce the DAC current by 50%.
NTSC PEDESTAL/PAL TELETEXT CONTROL
REGISTERS 3–0 (PCE15–0, PCO15–0)/ (TXE15–0, TXO15–0)
(Subaddress [SR4–SR0] = 11–0EH)
These 8-bit-wide registers are used to set up the NTSC pedes-
tal/PAL teletext on a line-by-line basis in the vertical blanking
interval for both odd and even fields. Figures 40 and 41 show
the four control registers. A Logic “1” in any of the bits of these
registers has the effect of turning the pedestal OFF on the
equivalent line when used in NTSC. A Logic “1” in any of the
bits of these registers has the effect of turning teletext ON the
equivalent line when used in PAL.
MR27
LOWER POWER
0
1
MODE
MR27
DISABLE
ENABLE
MR26
0
1
CONTROL
RGB/YUV
RGB OUTPUT
YUV OUTPUT
MR26
MR25
0
1
ENABLE BURST
DISABLE BURST
CONTROL
BURST
MR25
MR24
0
1
CHROMINANCE
CONTROL
ENABLE COLOR
DISABLE COLOR
MR24
MR23
0
1
ACTIVE VIDEO LINE WIDTH
MR23
MODE REGISTER 3 MR3 (MR37–MR30)
(Address [SR4–SR0] = 12H)
Mode Register 3 is an 8-bit-wide register.
Figure 42 shows the various operations under the control of
Mode Register 3.
MR3 BIT DESCRIPTION
Revision Code (MR30)
This bit is read only and indicates the revision of the device.
VBI Pass-Through (MR31)
This bit determines whether or not data in the vertical blanking
interval (VBI) is output to the analog outputs or blanked. VBI
Pass-Through is available in all timing modes except Slave 0.
Also when both VBI Pass-Through and BLANK input control
(TR03) are enabled, TR03 takes priority.
Reserved (MR33–MR32)
These bits are reserved.
Teletext Enable (MR34)
This bit must be set to “1” to enable teletext data insertion on
the TTX pin.
FIELD 1/3
FIELD 1/3
FIELD 1/3
FIELD 2/4
FIELD 2/4
FIELD 2/4
720 PIXELS
710/702 PIXELS
FIELD 1/3
FIELD 2/4
CONTROL
MR22 MR21
x
0
1
GENLOCK SELECTION
MR22
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15
0
1
1
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15
PCO15
PCE15
TXO15
TXE15
PCO7
PCE7
TXO7
TXE7
DISABLE GENLOCK
ENABLE SUBCARRIER
RESET PIN
ENABLE RTC PIN
PCO14
TXO14
PCE14
PCO6
TXE14
PCE6
TXO6
TXE6
MR21
PCO13
TXO13
PCO5
PCE13
TXE13
PCE5
TXO5
TXE5
MR20
SQUARE PIXEL
0
1
MR20
CONTROL
PCO12
TXO12
PCE12
PCO4
TXE12
PCE4
TXO4
TXE4
DISABLE
ENABLE
PCO11
TXO11
PCO3
PCE11
TXE11
PCE3
TXO3
TXE3
PCO10
PCE10
TXO10
TXE10
PCO2
PCE2
TXO2
TXE2
LINE 8
LINE 8 LINE 7
PCO9
PCO1
PCE1
PCE9
TXO1
TXO9
TXE1
TXE9
LINE 7
PCO0
PCO8
PCE0
PCE8
TXO0
TXO8
TXE0
TXE8