SAA7154E/V2/G,557 NXP Semiconductors, SAA7154E/V2/G,557 Datasheet - Page 32

• Manufacturer Part Number: SAA7154E/V2/G,557
• Manufacturer: NXP Semiconductors

Specifications of SAA7154E/V2/G,557

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SAA7154E_SAA7154H_2
Product data sheet
7.13.1 Power-on reset and chip enable input
7.12 I
7.13 Power and reset control
An other option is to use the second CGC for jitter removal from the frame-locked audio
clock generated inside the SAA7154E; SAA7154H.
Supported audio clock frequencies of the low jitter frame locked audio clock from the
audio master clock are (with f
Due to the number of new functions in the SAA7154E; SAA7154H, two I
addresses are required for full control of all registers. In order to auto control two decoder
devices independently, pin RTCO = logic 0 enables slave addresses (write) 42h and 4Ah
and pin RTCO = logic 1 enables slave addresses (write) 40h and 48h. For a read access,
addresses are incremented by one as usual.
Do not connect the output pin RTCO directly to ground or power supply. Use a pull-down
or pull-up resistor of 4.7 k instead.
A missing XTAL clock, insufficient digital or analog V
nominal 3.3 V pins and below 1.2 V for nominal 1.8 V supply pins) will start the reset
sequence. All outputs are forced to 3-state. The indicator output pin RES_N = logic 0 for
approximately 2000 XTAL cycles after the internal reset and can be applied to reset other
circuits of the digital TV system. The reset will release if the supply increases above 1.4 V
(for 1.8 V supply) and 2.5 V (3.3 V supply).
It is possible to force a reset by pulling the chip enable input (pin CE) to ground. After the
rising edge of CE and sufficient power supply voltage, the outputs LLC, LLC2_54 and
SDA return from 3-state to active, while the other signals have to be activated through
programming.
With this procedure the order of applying the different voltages is not important:
2
•
•
•
•
•
•
•
•
•
•
•
C-bus slave transmitter
256
384
512
Set CE = logic 1
Apply all supplies
Wait for 5 ms
Set CE = logic 0
Wait for 1 s
Set CE = logic 1
Wait for 1 ms
Start I
2
f
f
f
s
s
s
C-bus initialization.
.
Rev. 02 — 6 December 2007
s
= 32 kHz, 44.1 kHz or 48 kHz):
SAA7154E; SAA7154H
Multistandard video decoder with comb filter
DD
supply voltages (below 2.0 V for
© NXP B.V. 2007. All rights reserved.
2
C-bus slave
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