AD73460BB-80 Analog Devices Inc, AD73460BB-80 Datasheet
AD73460BB-80
Specifications of AD73460BB-80
Related parts for AD73460BB-80
AD73460BB-80 Summary of contents
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FEATURES AFE PERFORMANCE 6 16-Bit A/D Converters Programmable Input Sample Rate Simultaneous Sampling 72 dB SNR 64 kS/s Maximum Sample Rate –80 dB Crosstalk Low Group Delay (25 s Typ per ADC Channel) Programmable Input Gain Single Supply Operation ...
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AD73460 TABLE OF CONTENTS Topic FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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V to 3.6 V; DVDD = 3 3.6 V; DGND = AGND = SPECIFICATIONS kHz Parameter REFERENCE REFCAP Absolute Voltage, V REFCAP REFCAP TC REFOUT Typical Output ...
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AD73460–SPECIFICATIONS Parameter LOGIC INPUTS V , Input High Voltage INH V , Input Low Voltage INL I , Input Current Input Capacitance IN LOGIC OUTPUTS V , Output High Voltage Output Low Voltage OL ...
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V to 3.6 V; DVDD = 3 3.6 V; DGND = AGND = 0 V, SPECIFICATIONS f = 16.384 MHz, f MCLK Parameter DSP SECTION Hi-Level Input Voltage IH V Hi-Level CLKIN ...
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... Operating Temperature Range Industrial (B Version –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –20°C to +125°C Model AD73460BB-80 AD73460BB-40 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD73460 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...
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PBGA Ball PBGA Number Name Number IRQE/PF4 A1 E3 DMS VDD(INT CLKIN E6 A5 A11/IAD10 E7 A6 A7/IAD6 F1 A7 A4/IAD3 F2 IRQL0/PF5 B1 F3 PMS XTAL F6 B5 ...
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AD73460 Mnemonic Function VINP1 Analog Input to the Positive Terminal of Input Channel 1 VINN1 Analog Input to the Negative Terminal of Input Channel 1 VINP2 Analog Input to the Positive Terminal of Input Channel 2 VINN2 Analog Input to ...
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Mnemonic Function WR (Output) Memory Write Enable Output IRQ2/ (Input) Edge- or Level-Sensitive Interrupt PF7 (Input/Output) Request. IRQL0/ (Input) Level-Sensitive Interrupt Requests PF6 (Input/Output) Programmable I/O Pin IRQL1/ (Input) Level-Sensitive Interrupt Requests PF5 (Input/Output) Programmable I/O Pin IRQE/ (Input) Edge-Sensitive ...
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AD73460 ARCHITECTURE OVERVIEW The AD73460 instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instruc- tions. Every instruction can be executed in a single processor cycle. The AD73460 assembly language uses an algebraic ...
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VINP1 SIGNAL CONDITIONING VINN1 VINP2 SIGNAL CONDITIONING VINN2 VINP3 SIGNAL CONDITIONING VINN3 REFCAP REFOUT VINP4 SIGNAL CONDITIONING VINN4 VINP5 SIGNAL CONDITIONING VINN5 VINP6 SIGNAL CONDITIONING VINN6 Figure 2. Functional Block Diagram of Analog Front End FUNCTIONAL DESCRIPTION—AFE Encoder Channel Each ...
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AD73460 Analog Sigma-Delta Modulator The AD73460 input channels employ a sigma-delta conversion technique, which provides a high resolution 16-bit output with system filtering being implemented on-chip. Sigma-delta converters employ a technique known as over- sampling, where the sampling rate is ...
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ADC Coding The ADC coding scheme is in two’s complement format (see Figure 5). The output words are formed by the decimation filter, which grows the word length from the single-bit output of the sigma-delta modulator to a 15-bit word, ...
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AD73460 words to the AFE. In certain configurations, data can be written to the device to coincide with the output sample being shifted out of the serial register—see section on interfacing devices. The serial clock rate (CRB:2–3) defines how many ...
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Address (Binary) Name 000 CRA 001 CRB 010 CRC 011 CRD 100 CRE 101 CRF 110 CRG 111 CRH R/W DEVICE ADDRESS C/D Control Frame Bit 15 CONTROL/DATA Bit 14 READ/WRITE Bits 13–11 DEVICE ADDRESS ...
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AD73460 CONTROL REGISTER B 7 CEE Bit CONTROL REGISTER C RES Bit CONTROL REGISTER D PUI2 Bit ...
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CONTROL REGISTER E PUI4 Bit CONTROL REGISTER F PUI6 Bit CONTROL REGISTER G SEEN Bit REV. ...
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AD73460 CONTROL REGISTER H 7 INV Bit OPERATION Resetting the AFE The ARESET pin resets all the control registers. All the AFE registers are reset to zero, indicating that the default SCLK2 ...
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Data Mode Once the device has been configured by programming the cor- rect settings to the various control registers, the device may exit Program Mode and enter Data Mode. This is done by program- ming the DATA/PGM (CRA:0) bit to ...
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AD73460 In Cascade Mode, both devices must know the number of devices in the cascade to be able to output data at the correct time. Control Register A contains a 3-bit field (DC0–2) that is pro- grammed by the DSP ...
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A length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. Efficient data transfer is achieved with the use ...
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AD73460 Full Memory Mode Pins (Mode Pin # of Input/ Name(s) Pins Output Function A13 Address Output Pins for Program, Data, Byte, and I/O Spaces D23:0 24 I/O Data I/O Pins for Program, Data, Byte, ...
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Interrupts The interrupt controller allows the processor to respond to the 11 possible interrupts and RESET with minimum overhead. The AD73460 provides four dedicated external interrupt input pins, IRQ2, IRQL0, IRQL1, and IRQE. In addition, SPORT1 may be reconfigured for ...
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AD73460 When the IDLE (n) instruction is used, it effectively slows down the processor’s internal clock and thus its response time to incoming interrupts. The one-cycle response time of the stan- dard idle state is increased by n, the clock ...
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MODE C MODE B MODE NOTES All mode pins are recognized while RESET is active (low When Mode Full ...
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AD73460 Program Memory (Host Mode) allows access to all internal memory. External overlay access is limited by a single external address line (A0). External program execution is not available in host mode due to a restricted databus that is only ...
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The CMS pin functions like the other memory select signals, with the same timing and bus request logic the enable bit causes the assertion of the CMS signal at the same time as the selected memory select ...
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AD73460 DSP with only one DSP cycle per word overhead. The IDMA port cannot be used, however, to write to the DSP’s memory- mapped control registers. A typical IDMA transfer process is described as follows: 1. Host starts IDMA transfer. ...
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If the AD73460 is performing an external memory access when the external device asserts the BR signal, it will not three-state the memory interfaces nor assert the BG signal until the proces- sor cycle after the access completes. The instruction ...
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AD73460 The EZ-ICE uses the EE (emulator enable) signal to take control of the AD73460 in the target system. This causes the processor to use its ERESET, EBR, and EBG pins instead of the RESET, BR, and BG pins. The ...
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TFS SDIFS DT SCLK SCLK DSP DR SDO SECTION RFS SDOFS ARESET FL0 FL1 Figure 20. DSP to AD73460 AFE Connection CASCADE OPERATION Where it is required to configure an extra analog input channel to the existing six channels on ...
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AD73460 Figure 24 details the dc-coupled input circuits for single-ended operation respectively. 100 VINPx VIN VINNx 0.047 F REFOUT REFCAP 0.1 F Figure 24. Example Circuit for Single-Ended Input (DC Coupling) 14.00 BSC TOP VIEW 3.50 MAX 2.15 NOM Revision ...