AD73460BB-80 Analog Devices Inc, AD73460BB-80 Datasheet - Page 31

• Manufacturer Part Number: AD73460BB-80
• Manufacturer: Analog Devices Inc

Specifications of AD73460BB-80

• Analog Front End Type: General Purpose
• Analog Front End Category: General Purpose
• Interface Type: Digital
• Sample Rate: 64KSPS
• Input Voltage Range: 0.822V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 16b
• Supply Current: 54mA
• Number Of Adc's: 6
• Power Supply Type: Analog/Digital
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 119
• Package Type: BGA
• Number Of Channels: 6
• Lead Free Status / RoHS Status: Not Compliant

CASCADE OPERATION
Where it is required to configure an extra analog input channel
to the existing six channels on the AD73460, it is possible to
cascade six more channels (using external AD73360 AFEs) by
using the scheme described in Figure 22. It is necessary how-
ever to ensure that the timing of the SE and ARESET signals is
synchronized at each device in the cascade. A simple D-type
flip-flop is sufficient to synchronize each signal to the master
clock AMCLK as shown in Figure 21.
There may be some restrictions in cascade operation due to the
number of devices configured in the cascade and the serial clock
rate chosen. The formula below gives an indication of whether
the combination of sample rate and serial clock can be success-
fully cascaded. This assumes a directly coupled frame sync
arrangement as shown in Figure 20 and does not take any interrupt
latency into account.
When using the indirectly coupled frame sync configuration in
cascaded operation, it is necessary to be aware of the restrictions
in sending control word data to all devices in the cascade. The
user should ensure that there is sufficient time for all the control
words to be sent between reading the last ADC sample and the
start of the next sample period.
Connection of a cascade, as shown in Figure 22, is no more
complicated than connecting a single device. Instead of connect-
ing the SDO and SDOFS to the DSP’s Rx port, these are now
daisy-chained to the SDI and SDIFS of the next device in the
cascade. The SDO and SDOFS of the final device in the cascade
REV. A
Figure 21. SE and ARESET Sync Circuit for Cascaded
Operation
DSP CONTROL
TO ARESET
DSP CONTROL
TO SE
AMCLK
AMCLK
Figure 20. DSP to AD73460 AFE Connection
SECTION
DSP
f
1
S
≥
6
×
[((
TFS
DT
SCLK
DR
RFS
FL0
FL1
CLK
CLK
D
D
74HC74
74HC74
Device Count
1/2
1/2
Q
Q
SCLK
SE SIGNAL SYNCHRONIZED
TO AMCLK
ARESET SIGNAL SYNCHRONIZED
TO AMCLK
ARESET
SDOFS
SDIFS
SCLK
−
SDO
SDI
1
SE
)
×
16
)
SECTION
+
AFE
17
]
–31–
are connected to the DSP’s Rx port to complete the cascade. SE
and ARESET on all devices are fed from the signals that were
synchronized with the AMCLK using the circuit of Figure 21.
The SCLK from only one device needs to be connected to the
DSP’s SCLK input(s) as both devices will be running at the same
SCLK frequency and phase.
Interfacing to the AFE’s Analog Inputs
The AD73460 features six signal conditioning inputs. Each
signal conditioning block allows the AD73460 to be used with
either a single-ended or differential signal. The applied signal
can also be inverted internally by the AD73460 if required. The
analog input signal to the AD73460 can be dc-coupled, provided
that the dc bias level of the input signal is the same as the internal
reference level (REFOUT). Figure 23 shows the recommended
differential input circuit for the AD73460. The circuit of Figure
23 implements first-order low-pass filters with a 3 dB point at
34 kHz; these are the only filters that must be implemented
external to the AD73460 to prevent aliasing of the sampled
signal. Since the ADC uses a highly oversampled approach
that transfers the bulk of the antialiasing filtering into the digital
domain, the off-chip antialiasing filter need only be of a low
order. It is recommended that for optimum performance, the
capacitors used for the antialiasing filter be of high quality
dielectric (NPO).
Figure 22. Connection of an AD73360 Cascaded to the
AD73460
FL0
VIN
SECTION
TO INPUT BIAS
Figure 23. Example Circuit for Differential Input
(DC Coupling)
DSP
FL1
CIRCUITRY
D1
D0
100
100
0.047 F
TFS
DT
SCLK
DR
RFS
74HC74
AD73460
CLK
0.1 F
Q0
Q1
0.047 F
REFOUT
SDOFS
SDOFS
SDIFS
SDIFS
SCLK
SCLK
SDO
SDO
SDI
SDI
REFCAP
VINPx
VINNx
ADDITIONAL
DEVICE 2
DEVICE 1
AD73360
AFE
AFE
AD73460
REFERENCE
VOLTAGE
AMCLK
SE
ARESET
MCLK
SE
RESET