UDA1343TT NXP Semiconductors, UDA1343TT Datasheet - Page 22

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UDA1343TT

Manufacturer Part Number
UDA1343TT
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of UDA1343TT

Single Supply Voltage (typ)
3V
Single Supply Voltage (min)
2.4V
Single Supply Voltage (max)
3.6V
Package Type
TSSOP
Lead Free Status / RoHS Status
Not Compliant

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Philips Semiconductors
DC
A 1-bit value to enable the digital DC filter (see Table 24).
Table 24 DC filtering; note 1
Note
1. The corner frequencies of the DC filter are given assuming 44.1 kHz sampling frequency.
ADC
Three 1-bit value to disable the ADC to reduce power consumption.
Table 25 Power control settings
PGA
Two 4-bit values to program the PGA gain settings. The PGA settings can be set individually for the left and the right
channels.
Table 26 PGA gain control settings
2001 Jul 25
PON BIAS
Economy audio CODEC with features
PGAL3, PGAR3
FILTER
POWER CONTROL
GAIN SETTINGS
0
1
1
1
DC1
0
0
1
1
0
0
0
0
0
0
0
0
1
1
PON-R ADC
0
1
1
x
PGAL2, PGAR2
PON-L ADC
DC0
0
1
0
1
0
0
0
0
1
1
1
1
0
:
x
1
0
1
no DC filtering
DC filtering with 3 dB at 3 Hz
DC filtering with 3 dB at 100 Hz
DC filtering with 3 dB at 200 Hz
both ADC channels off and also bias block turned off
ADC left channel powered on, bias block turned on
ADC right channel powered on, bias block turned on
both left and right ADC channels enabled, bias block turned on
PGAL1, PGAR1
22
0
0
1
1
0
0
1
1
0
:
PGAL0, PGAR0
FUNCTION
FUNCTION
0
1
0
1
0
1
0
1
0
:
UDA1343TT
Product specification
FUNCTION
12 dB gain
15 dB gain
18 dB gain
21 dB gain
24 dB gain
0 dB gain
3 dB gain
6 dB gain
9 dB gain
not used

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