ADAV803AST Analog Devices Inc, ADAV803AST Datasheet - Page 32
ADAV803AST
Manufacturer Part Number
ADAV803AST
Description
Manufacturer
Analog Devices Inc
Datasheet
1.ADAV803AST.pdf
(60 pages)
Specifications of ADAV803AST
Single Supply Voltage (typ)
3.3V
Single Supply Voltage (min)
3V
Single Supply Voltage (max)
3.6V
Package Type
LQFP
Lead Free Status / RoHS Status
Not Compliant
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ADAV803
REGISTER DESCRIPTIONS
SRC and Clock Control—Address 0000000 (0x00)
Table 17. SRC and Clock Control Register Bit Map
7
SRCDIV1
Table 18. SRC and Clock Control Register Bit Descriptions
Bit Name
SRCDIV[1:0]
CLK2DIV[1:0]
CLK1DIV[1:0]
MCLKSEL[1:0]
S/PDIF Loopback Control—Address 0000011 (0x03)
Table 19. S/PDIF Loopback Control Register Bit Map
7
Reserved
Table 20. S/PDIF Loopback Control Register Bit Descriptions
Bit Name
TxMUX
6
SRCDIV0
6
Reserved
Description
Divides the SRC master clock.
Clock divider for Internal Clock 2 (ICLK2).
Clock divider for Internal Clock 1 (ICLK1).
Clock selection for the SRC master clock.
Description
Selects the source for S/PDIF output (DITOUT).
00 = SRC master clock is not divided.
01 = SRC master clock is divided by 1.5.
10 = SRC master clock is divided by 2.
11 = SRC master clock is divided by 3.
00 = Divide by 1.
01 = Divide by 1.5.
10 = Divide by 2.
11 = Divide by 3.
00 = Divide by 1.
01 = Divide by 1.5.
10 = Divide by 2.
11 = Divide by 3.
00 = Internal Clock 1.
01 = Internal Clock 2.
10 = PLL recovered clock (512 × f
11 = PLL recovered clock (256 × f
0 = S/PDIF transmitter, normal mode.
1 = DIRIN, loopback mode.
5
CLK2DIV1
5
Reserved
4
CLK2DIV0
4
Reserved
S
S
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Rev. A | Page 32 of 60
3
CLK1DIV1
3
Reserved
2
CLK1DIV0
2
Reserved
1
MCLKSEL1
1
Reserved
0
MCLKSEL0
0
TxMUX