ADAV803AST Analog Devices Inc, ADAV803AST Datasheet - Page 41

• Manufacturer Part Number: ADAV803AST
• Manufacturer: Analog Devices Inc

Specifications of ADAV803AST

• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: LQFP
• Lead Free Status / RoHS Status: Not Compliant

Receiver Error—Address 0011000 (0x18)
Table 61. Receiver Error Register (Read-Only) Bit Map
7
RxValidity
Table 62. Receiver Error Register (Read-Only) Bit Descriptions
Bit Name
RxValidity
Emphasis
NonAudio
NonAudio
Preamble
CRCError
NoStream
BiPhase/Parity
Lock
Receiver Error Mask—Address 0011001 (0x19)
Table 63. Receiver Error Mask Register Bit Map
7
RxValidity
Mask
Table 64. Receiver Error Mask Register Bit Descriptions
Bit Name
RxValidity Mask
Emphasis Mask
NonAudio Mask
NonAudio Preamble Mask
CRCError Mask
NoStream Mask
BiPhase/Parity Mask
Lock Mask
6
Emphasis
6
Emphasis
Mask
Description
This is the VALIDITY bit in the AES3 received stream.
This bit is set if the audio data is pre-emphasized. Once it has been read, it remains high and does not generate an
interrupt unless it changes state.
This bit is set when Channel Status Bit 1 (nonaudio) is set. Once it has been read, it does not generate another interrupt
unless the data becomes audio or the type of nonaudio data changes.
This bit is set if the audio data is nonaudio due to the detection of a preamble. The nonaudio preamble type register
indicates what type of preamble was detected. Once read, it remains in its state and does not generate an interrupt
unless it changes state.
This bit is the error flag for the channel status CRCError check. This bit does not clear until the receiver error register is read.
This bit is set if there is no AES3/S/PDIF stream present at the AES3/S/PDIF receiver. Once read, it remains high and does
not generate an interrupt unless it changes state.
This bit is set if the PLL has locked or cleared when the PLL loses lock. Once read, it remains in its state and does not
generate an interrupt unless it changes state.
This bit is set if a biphase or parity error occurred in the AES3/S/PDIF stream. This bit is not cleared until the register is read.
Description
Masks the RxValidity bit from generating an interrupt.
Masks the Emphasis bit from generating an interrupt.
Masks the NonAudio bit from generating an interrupt.
Masks the NonAudio preamble bit from generating an interrupt.
Masks the CRCError bit from generating an interrupt.
Masks the NoStream bit from generating an interrupt.
Masks the BiPhase/Parity bit from generating an interrupt.
Masks the Lock bit from generating an interrupt.
5
NonAudio
5
NonAudio
Mask
0 = RxValidity bit does not generate an interrupt.
1 = RxValidity bit generates an interrupt.
0 = Emphasis bit does not generate an interrupt.
1 = Emphasis bit generates an interrupt.
0 = NonAudio bit does not generate an interrupt.
1 = NonAudio bit generates an interrupt.
0 = NonAudio preamble bit does not generate an interrupt.
1 = NonAudio preamble bit generates an interrupt.
0 = CRCError bit does not generate an interrupt.
1 = CRCError bit generates an interrupt.
0 = NoStream bit does not generate an interrupt.
1 = NoStream bit generates an interrupt.
0 = BiPhase/Parity bit does not generate an interrupt.
1 = BiPhase/Parity bit generates an interrupt.
0 = Lock bit does not generate an interrupt.
1 = Lock bit generates an interrupt.
4
NonAudio Preamble
Mask
4
NonAudio Preamble
Rev. A | Page 41 of 60
3
CRCError
Mask
3
CRCError
2
NoStream
Mask
2
NoStream
1
BiPhase/Parity
Mask
1
BiPhase/Parity
ADAV803
0
Lock
Mask
0
Lock