AD1847JP Analog Devices Inc, AD1847JP Datasheet - Page 12
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AD1847JP
Manufacturer Part Number
AD1847JP
Description
Manufacturer
Analog Devices Inc
Datasheet
1.AD1847JP.pdf
(28 pages)
Specifications of AD1847JP
Single Supply Voltage (typ)
5V
Single Supply Voltage (min)
4.75V
Single Supply Voltage (max)
5.25V
Package Type
PLCC
Lead Free Status / RoHS Status
Not Compliant
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Company
Part Number
Manufacturer
Quantity
Price
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Manufacturer:
AD
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Manufacturer:
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AD1847
Index Readback (16-Bit)
DATA7:0 Index Register Data. These bits are the readback data from the desired AD1847 Index Register referenced by the Index
IA3:0
RREQ
res
MCE
CLOR
Immediately after reset, the contents of this register is: 1110 0000 0000 0000 (E000h).
Indirect Mapped Registers
Following in Figure 6 is a table defining the mapping of AD1847 8-bit Index Registers to Index Address. These registers are accessed
by writing the appropriate 4-bit Index Address in the Control Word.
A detailed description of each of the Index Registers is given below.
Data 15
DATA7
Data 7
CLOR
Address from the previous Control Word (with the RREQ bit set). Read by the host CPU or DSP from the AD1847.
Index Register Address. These bits echo the indirect address (written during the previous Control Word (with the RREQ
bit set) of the desired AD1847 Index Register to be readback. Read by the host CPU or DSP from the AD1847.
Read Request. This bit is set HI for Index Readback, echoing the RREQ state written by the host CPU or DSP in the
previous Control Word. Read by the host CPU or DSP from the AD1847.
Reserved for future expansion. All reserved bits read zero (LO).
Mode Change Enable. This bit echoes the MCE state written by the host CPU or DSP during the previous* Control
Word (with the RREQ bit set). Read by the host CPU or DSP from the AD1847.
Clear Overrange. This bit echoes the CLOR state written by the host CPU or DSP during the previous Control Word
(with the RREQ bit set). Read by the host CPU or DSP from the AD1847.
Data 14
DATA6
Data 6
MCE
Data 13
DATA5
Data 5
RREQ
Index
10
11
12
13
14
15
Figure 6. Index Register Mapping
0
1
2
3
4
5
6
7
8
9
Data 12
DATA4
Data 4
Register Name
res
Left Input Control
Right Input Control
Left Aux #1 Input Control
Right Aux #l Input Control
Left Aux #2 Input Control
Right Aux #2 Input Control
Left DAC Control
Right DAC Control
Data Format
Interface Configuration
Pin Control
Invalid Address
Miscellaneous Information
Digital Mix Control
Invalid Address
Invalid Address
–12–
Data 11
DATA3
Data 3
IA3
Data 10
DATA2
Data 2
IA2
DATA1
Data 9
Data 1
IA1
DATA0
Data 8
Data 0
IA0
REV. B