AD1847JP Analog Devices Inc, AD1847JP Datasheet - Page 25
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AD1847JP
Manufacturer Part Number
AD1847JP
Description
Manufacturer
Analog Devices Inc
Datasheet
1.AD1847JP.pdf
(28 pages)
Specifications of AD1847JP
Single Supply Voltage (typ)
5V
Single Supply Voltage (min)
4.75V
Single Supply Voltage (max)
5.25V
Package Type
PLCC
Lead Free Status / RoHS Status
Not Compliant
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Part Number
Manufacturer
Quantity
Price
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AD
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REV. B
The crystals shown in the crystal connection circuitry of Figure
21 should be fundamental-mode and parallel-tuned. Two
sources for the exact crystals specified are Component Market-
ing Services in Massachusetts, U.S. at 617/762-4339 and
Cardinal Components in New Jersey, U.S. at 201/746-0333.
Note that using the exact data sheet frequencies is not required
and that external clock sources can be used to overdrive the
AD1847s internal oscillators. (See the description of the CFS2:0
control bits above.) If using an external clock source, apply it to
the crystal input pins while leaving the crystal output pins un-
connected. Attention should be paid to providing low-jitter ex-
ternal input clocks .
Analog Devices also recommends a pull-down resistor on the
PWRDOWN signal.
Good, standard engineering practices should be applied for
power-supply decoupling. Decoupling capacitors should be
placed as close as possible to package pins. If a separate analog
power supply is not available, the circuit shown in Figure 22 is
recommended when using a single +5 V supply. Ferrite beads
suffice for the inductors shown. This circuitry should be as close
to the supply pins as is practical.
+5V SUPPLY
Figure 22. Recommended Power Supply Bypassing
20 64pF
XTAL1I
24.576MHz
Figure 21. Crystal Connections
FERRITE
0.1 F
0.1 F
FERRITE
XTAL1O
20 64pF
1 F
1 F
V
DD
1.6
20 64pF
0.1 F
V
1 F
DD
XTAL2I
0.1 F
16.9344MHz
0.1 F
V
DD
XTAL2O
V
0.1 F
CC
V
20 64pF
V
DD
CC
0.1 F
–25–
Analog Devices recommends a split ground plane as shown in
Figure 23. The analog plane and the digital plane are connected
directly under the AD1847. Splitting the ground plane directly
under the SoundPort Codec is optimal because analog pins will
be located directly above the analog ground plane and digital
pins will be located directly above the digital ground plane for
the best isolation. The digital and analog grounds should be tied
together in the vicinity of the AD1847. Other schemes may also
yield satisfactory results. If the split ground plane recommended
here is not possible, the AD1847 should be entirely over the
analog ground plane with the ASIC and DSP over the digital
plane.
DIGITAL
GROUND
PLANE
Figure 23. Recommended Ground Plane
PWRDOWN
AD1847
BM
L_AUX2
V
CC
AD1847
GROUND
ANALOG
PLANE