AD73422BB-40 Analog Devices Inc, AD73422BB-40 Datasheet - Page 28

• Manufacturer Part Number: AD73422BB-40
• Manufacturer: Analog Devices Inc

Specifications of AD73422BB-40

• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: BGA
• Lead Free Status / RoHS Status: Not Compliant

AD73422
Composite Memory Select (CMS)
The AD73422 has a programmable memory select signal that is
useful for generating memory select signals for memories mapped
to more than one space. The CMS signal is generated to have
the same timing as each of the individual memory select signals
(PMS, DMS, BMS, IOMS) but can combine their functionality.
Each bit in the CMSSEL register, when set, causes the CMS
signal to be asserted when the selected memory select is as-
serted. For example, to use a 32K word memory to act as both
program and data memory, set the PMS and DMS bits in the
CMSSEL register and use the CMS pin to drive the chip select
of the memory; use either DMS or PMS as the additional
address bit.
The CMS pin functions like the other memory select signals,
with the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the CMS signal at the same time as the
selected memory select signal. All enable bits default to 1 at
reset, except the BMS bit.
Boot Memory Select (BMS) Disable
The AD73422 also lets you boot the processor from one exter-
nal memory space while using a different external memory space
for BDMA transfers during normal operation. You can use the
CMS to select the first external memory space for BDMA trans-
fers and BMS to select the second external memory space for
booting. The BMS signal can be disabled by setting Bit 3 of the
System Control Register to 1. The System Control Register is
illustrated in Figure 17.
Byte Memory
The byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The BDMA Control Regis-
ter is shown in Figure 18. The byte memory space consists of
256 pages, each of which is 16K × 8.
The byte memory space on the AD73422 supports read and
write operations as well as four different data formats. The byte
memory uses data bits 15:8 for data. The byte memory uses
data bits 23:16 and address bits 13:0 to create a 22-bit address.
This allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be
used without glue logic. All byte memory accesses are timed by
the BMWAIT register.
SPORT0 ENABLE
SPORT1 ENABLE
SPORT1 CONFIGURE
1 = ENABLED
0 = DISABLED
1 = ENABLED
0 = DISABLED
1 = SERIAL PORT
0 = FI, FO, IRQ0,
IRQ1, SCLK
15 14 13 12 11 10 9
0
0
0
Address Range Wait State Register
0x000–0x1FF
0x200–0x3FF
0x400–0x5FF
0x600–0x7FF
Figure 17. System Control Register
0
SYSTEM CONTROL REGISTER
0
Table XXIV. Wait States
1
0
8
0
7
0
IOWAIT0
IOWAIT1
IOWAIT2
IOWAIT3
6
0
5
0
4
0
3
0
2
1
1
1
PWAIT
PROGRAM MEMORY
WAIT STATES
BMS ENABLE
0
1
0 = ENABLED
1 = DISABLED
DM (0 3FFF)
–28–
Byte Memory DMA (BDMA, Full Memory Mode)
The Byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space.
The BDMA circuit is able to access the byte memory space
while the processor is operating normally, and steals only one
DSP cycle per 8-, 16- or 24-bit word transferred.
The BDMA circuit supports four different data formats that are
selected by the BTYPE register field. The appropriate number
of 8-bit accesses are done from the byte memory space to build
the word size selected. Table XXV shows the data formats sup-
ported by the BDMA circuit.
BTYPE
00
01
10
11
Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address
for the on-chip memory involved with the transfer. The 14-bit
BEAD register specifies the starting address for the external
byte memory space. The 8-bit BMPAGE register specifies the
starting page for the external byte memory space. The BDIR
register field selects the direction of the transfer. Finally the
14-bit BWCOUNT register specifies the number of DSP words
to transfer and initiates the BDMA circuit transfers.
BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT register.
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches
zero, the transfers have finished and a BDMA interrupt is gener-
ated. The BMPAGE and BEAD registers must not be accessed
by the DSP during BDMA operations.
The source or destination of a BDMA transfer will always be
on-chip program or data memory.
When the BWCOUNT register is written with a nonzero value,
the BDMA circuit starts executing byte memory accesses with
wait states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to
create a destination word, it is transferred to or from on-chip
memory. The transfer takes one DSP cycle. DSP accesses to exter-
nal memory have priority over BDMA byte memory accesses.
15 14 13 12 11 10 9
0
0
0
BMPAGE
0
Figure 18. BDMA Control Register
Internal
Memory Space
Program Memory
Data Memory
Data Memory
Data Memory
0
Table XXV. Data Formats
0
BDMA CONTROL
0
8
0
7
0
6
0
5
0
4
0
Word Size
24
16
8
8
3
1
2
0
BCR
0 = RUN DURING BDMA
1 = HALT DURING BDMA
BTYPE
1
0
BDIR
0 = LOAD FROM BM
1 = STORE TO BM
0
0
DM (0 3FE3)
Alignment
Full Word
Full Word
MSBs
LSBs
REV. 0