AD73422BB-40 Analog Devices Inc, AD73422BB-40 Datasheet - Page 9

• Manufacturer Part Number: AD73422BB-40
• Manufacturer: Analog Devices Inc

Specifications of AD73422BB-40

• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: BGA
• Lead Free Status / RoHS Status: Not Compliant

ARCHITECTURE OVERVIEW
The AD73422 instruction set provides flexible data moves and
multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single pro-
cessor cycle. The AD73422 assembly language uses an algebraic
syntax for ease of coding and readability. A comprehensive set
of development tools supports program development.
Figure 1 is an overall block diagram of the AD73422. The pro-
cessor section contains three independent computational units:
the ALU, the multiplier/accumulator (MAC) and the shifter.
The computational units process 16-bit data directly and have
provisions to support multiprecision computations. The ALU
performs a standard set of arithmetic and logic operations; divi-
sion primitives are also supported. The MAC performs single-
cycle multiply, multiply/add and multiply/subtract operations
with 40 bits of accumulation. The shifter performs logical and
arithmetic shifts, normalization, denormalization and derive
exponent operations.
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. The sequencer supports conditional jumps, sub-
routine calls and returns in a single cycle. With internal loop
counters and loop stacks, the AD73422 executes looped code
with zero overhead; no explicit jump instructions are required to
maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four possible modify registers. A length value may be associated
with each pointer to implement automatic modulo addressing
for circular buffers.
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
REV. 0
GENERATORS
DAG 1
ADDRESS
ALU
DATA
ARITHMETIC UNITS
ADSP-2100 BASE
ARCHITECTURE
DAG 2
MAC
Figure 1. Functional Block Diagram
SEQUENCER
PROGRAM
SHIFTER
DATA MEMORY DATA
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
REF
ADC1
(OPTIONAL
SPORT 0
16K PM
ANALOG FRONT END
SERIAL PORTS
POWER-DOWN
8K)
DAC1
CONTROL
MEMORY
SERIAL PORT
SECTION
SPORT 2
SPORT 1
(OPTIONAL
16K DM
8K)
ADC2
TIMER
PROGRAMMABLE
DAC2
FLAGS
AND
I/O
FULL MEMORY
CONTROLLER
HOST MODE
EXTERNAL
EXTERNAL
EXTERNAL
BYTE DMA
ADDRESS
INTERNAL
MODE
DATA
DATA
PORT
BUS
DMA
BUS
BUS
OR
–9–
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
The AD73422 can respond to eleven interrupts. There can be
up to six external interrupts (one edge-sensitive, two level-
sensitive and three configurable) and seven internal interrupts
generated by the timer, the serial ports (SPORTs), the Byte
DMA port and the power-down circuitry. There is also a master
RESET signal. The two serial ports provide a complete synchro-
nous serial interface with optional companding in hardware and
a wide variety of framed or frameless data transmit and receive
modes of operation.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
The AD73422 provides up to 13 general-purpose flag pins. The
data input and output pins on SPORT1 can be alternatively
configured as an input flag and an output flag. In addition, eight
flags are programmable as inputs or outputs and three flags are
always outputs.
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) is decremented every n pro-
cessor cycle, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Analog Front End
The AFE section is configured as a separate block that is nor-
mally connected to either SPORT0 or SPORT1 of the DSP
section. As it is not hardwired to either SPORT, the user has
total flexibility in how they wish to allocate system resources to
support the AFE. It is also possible to further expand the num-
ber of analog I/O channels connected to the SPORT by cascad-
ing other single or dual channel AFEs (AD73311 or AD73322)
external to the AD73422.
The AFE is configured as a cascade of two I/O channels (similar
to that of the discrete AD73322—refer to the AD73322 data sheet
for more details), with each channel having a separate 16-bit
sigma-delta based ADC and DAC. Both channels share a com-
mon reference whose nominal value is 1.2 V. Figure 2 shows a
block diagram of the AFE section of the AD73422. It shows two
channels of ADC and DAC conversion, along with a common
reference. Communication to both channels is handled by the
SPORT2 block which interfaces to either SPORT0 or SPORT1 of
the DSP section.
Figure 3 shows the analog connectivity available on each chan-
nel of the AFE (Channel 1 is detailed here). Both channels
feature fully differential inputs and outputs. The input section
allows direct connection to the internal Programmable Gain
Amplifier at the input of the sigma-delta ADC section, or op-
tional inverting amplifiers may be configured to provide some
fixed external gain or to interface to a transducer with relatively
high source impedance. The input section also features pro-
grammable differential channel inversion and configuration of
the differential input as two separate single-ended inputs. The
ADC features a second order sigma-delta modulator which
AD73422