NQ41210 S L7JE Intel, NQ41210 S L7JE Datasheet
NQ41210 S L7JE
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NQ41210 S L7JE Summary of contents
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... Intel® 41210 Serial to Parallel PCI Bridge Datasheet Product Features PCI Express Specification, Revision 1.0a Support for single x8, single x4 or single x1 PCI Express operation. 64-bit addressing support 32-bit CRC (cyclic redundancy checking) covering all transmitted data packets. 16-bit CRC on all link message information ...
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... Intel may make changes to specifications and product descriptions at any time, without notice. The Intel® 41210 Serial to Parallel PCI Bridge may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. ...
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Contents 1 Introduction.................................................................................................................................... 7 1.1 About This Document ........................................................................................................... 7 1.2 Product Overview ................................................................................................................. 7 2 Signal Description ......................................................................................................................... 8 2.1 On Die Termination (ODT).................................................................................................... 8 2.2 PCI Express Interface.........................................................................................................10 2.3 PCI Bus Interface (Two Instances) .....................................................................................10 2.4 PCI Bus ...
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... Reset Strap Pins......................................................................................................................... 14 8 SMBus Interface Pins ................................................................................................................. 15 9 Miscellaneous Pins ..................................................................................................................... 15 10 Intel® 41210 Bridge DC Voltage Specifications ......................................................................... Characteristics Input Signal Association .............................................................................. Input Characteristics............................................................................................................. Characteristic Output Signal Association ............................................................................. Output Characteristic............................................................................................................ 19 15 Differential Transmitter (TX) DC Output Specifications .............................................................. 19 16 Differential Receiver (RX) DC Input Specifications .................................................................... Specifications for PCI and PCI-X 3 ...
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Revision History Date Revision May 2005 005 Revised April 2005 004 Revised September 2004 003 Revised first page PCI Express operation description; updated information in Table 2. Added Chapter 2. Removed original Sections 3.6 and 3.7. Updated VCC information to ...
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Order Number: 278875-005US May 2005 ...
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... Product Overview The Intel® 41210 Serial to Parallel PCI Bridge (also called the 41210 Bridge) integrates two PCI Express-to-PCI/PCI-X bridges. Each bridge follows the PCI-to-PCI Bridge programming model. The PCI Express port is compatible with the PCI Express Specification, Revision 1.0a. The two PCI bus interfaces are compatible with the PCI Local Bus Specification, Revision 2 ...
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Bridge — Datasheet Signal Description The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal low voltage level. When “#” is not present after the ...
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Table 1. ODT Signals A_ACK64# A_AD[63:32] A_CBE#[7:4] A_DEVSEL# A_FRAME# A_GNT#[5:0] A_IRDY# A_PAR A_PAR64 A_PERR# A_LOCK# A_REQ#[5:0] A_REQ64# A_SERR# A_STOP# A_TRDY# A_INTA# A_INTB# A_INTC# A_INTD# TCK TDI TDO TMS Datasheet — 41210 Bridge B_ACK64# B_AD[63:32] B_CBE#[7:4] B_DEVSEL# B_FRAME# B_GNT#[5:0] B_IRDY# B_PAR ...
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Bridge — Datasheet 2.2 PCI Express Interface Table 2. PCI Express Interface Pins Signal REFCLKp/ REFCLKn PETp[7:0]/ PETn[7:0] PERp[7:0]/ PERn[7:0] PE_RCOMP[1:0] Total 2.3 PCI Bus Interface (Two Instances) Each interface is marked by either the letter “A” or “B” ...
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Table 3. PCI Interface Pins (Sheet Signal I/O PCI Address/Data: These signals are a multiplexed address and data bus. During the address phase or phases of a transaction, the initiator drives a physical address on X_AD[31:0]. During ...
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Bridge — Datasheet Table 3. PCI Interface Pins (Sheet Signal I/O A_PCIXCAP PCI-X Capable: Indicates whether all devices on the PCI bus are PCI-X devices, so that the I Bridge B_PCIXCAP can switch into PCI-X mode. ...
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... A_INTB# A_INTC# Interrupt Request Bus: The interrupt lines from PCI interrupts INTA#:INTD# can be routed to these A_INTD# interrupt lines. I B_INTA# Refer to the Intel® 41210 Serial to Parallel PCI Bridge Design Guide for more information on device B_INTB# numbering. B_INTC# B_INTD# Total 8 2.7 Reset Straps The following signals are used for static configuration ...
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... Configuration Retry: This pin, when sampled high sets the Configuration Cycle Retry Bit (bit 3) in the Bridge Initialization Register at Offset FC local initialization is needed, this pin should be pulled low to VSS. I Refer to the Intel® 41210 Serial to Parallel PCI Bridge Design Guide for more information. 19 Description resistor to pull-up to VCC33 or pull-down to resistor to pull-up to VCC33 ...
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... RSTIN#, or PCI Express Reset). This signal should be used to indicate when the local initialization methods should be O executed. Refer to the Intel® 41210 Serial to Parallel PCI Bridge Design Guide for more information. PCI Express Fundamental Reset: When low, asynchronously resets the I internal logic (including sticky bits) ...
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Bridge — Datasheet Signal TMS TRST# RESERVED[8:1] NC[19:18], NC[16:1] A_NC[10:1] B_NC[10:1] NC[17] Total 16 I/O Test Mode Select: This signal controls the TAP controller state machine to I move to different states and is sampled on the rising edge ...
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... DC Voltage and Current Specifications 3.1.1 41210 Bridge DC Specifications ® Table 10. Intel 41210 Bridge DC Voltage Specifications Symbol VCC15 Intel VCC15 PCI-X I/O Voltage VCCAPE Analog PCI Express Voltage VCCAPCI[2:0] Analog PCI Voltages VCCBGPE Analog Bandgap Voltage VCCPE PCI Express Interface Voltage ...
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Bridge — Datasheet 3.1.2 Input Characteristic Signal Association Table 11. DC Characteristics Input Signal Association Symbol Interrupt Signals: A_IRQ[15:0]#, B_IRQ[15:0]# PCI Signals: A_AD[63:0], B_AD[63:0], A_CBE[7:0]#, B_CBE[7:0]#, A_PAR, B_PAR, A_DEVSEL#, B_DEVSEL#, A_FRAME#, B_FRAME#, A_IRDY#, B_IRDY#, A_TRDY#, B_TRDY#, A_STOP#, B_STOP#, A_PERR#, ...
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DC Output Characteristics Table 14. DC Output Characteristic Symbol Parameter V Output Low Voltage OL1 V Output High Voltage OH1 Symbol Parameter V Output Low Voltage OL2 V Output High Voltage OH2 V Output Low Voltage OL3 V Output ...
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Bridge — Datasheet Table 15. Differential Transmitter (TX) DC Output Specifications (Sheet Absolute Delta Common Mode TX-CM-DC- Voltage between D+ LINE-DELTA and D-. Electrical Idle V TX-IDLE- Differential Peak DIFFp Output Voltage The ...
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Differential Receiver (RX) DC Input Specifications Table 16 defines the DC specifications of parameters for all differential Receivers (RXs). The parameters are specified at the component pins. Table 16. Differential Receiver (RX) DC Input Specifications Symbol Parameter Differential Input ...
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Bridge — Datasheet Figure 1. Minimum Transmitter Timing and Voltage Output Compliance Specification There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in time using the jitter median to locate ...
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Figure 2. Compliance Test/Measurement Load The test load is shown at the transmitter package reference plane, but the same Test/Measurement load is applicable to the receiver package reference plane. CTX is an optional portion of the measurement test load. The ...
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Bridge — Datasheet 3.1.6.4 PCI and PCI-X Interface DC Specifications Table 17 summarizes the DC specifications for 3.3V signaling. Table 17. DC Specifications for PCI and PCI-X 3.3 V Signaling Symbol Parameter VCC33 Supply Voltage V Input High Voltage ...
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Input Clock DC Specifications Table 18. DC Specification for Input Clock Signals Symbol CLK100 Input Low Voltage CLK100 Input High Voltage CLK133 Input Low Voltage CLK133 Input High Voltage 3.1.6.6 Output Clock DC Specifications Table 19. DC Specification for ...
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Bridge — Datasheet Table 20. Conventional PCI 3.3V AC Characteristics (Sheet Low Clamp Current cl slew Output Rise Slew r Rate slew Output Fall Slew f Rate 1. In conventional PCI switching, current characteristics for ...
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This parameter interpreted as the cumulative edge rate across the specified range rather than the instantaneous rate at any point within the transition range. For more details on slew rate measurement conditions please refer to the ...
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Bridge — Datasheet 3.5 Timing Specifications 3.5.1 PCI Express Interface Timing 3.5.1.1 Differential Transmitter (TX) AC Output Specifications Table 22 defines the AC specifications of parameters for the differential output at all transmitters (TXs). The parameters are specified at ...
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Measured between 20-80% at Transmitter package pins into a test load as shown in and V TX-D-. 3.5.1.2 Differential Receiver (RX) AC Input Specifications Table 23 defines the AC specifications of parameters for all differential Receivers (RXs). The parameters ...
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Bridge — Datasheet 3.5.2 PCI and PCI-X Interface Timing Table 24. PCI Interface Timing Functional Operating Range (VCC33 = 3 5%, Tcase 105 C) Symbol CLK to Signal Valid Delay; T val bused signals CLK ...
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Figure 5. PCI Output Timing Figure 6. PCI Input Timing Table 25. PCI-X 3.3V Signal Timing Parameters (Sheet Sym T CLK to Signal Valid Delay val Parameter PCI-X 133 Min Max 0.7 3.8 Datasheet — 41210 Bridge ...
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Bridge — Datasheet Table 25. PCI-X 3.3V Signal Timing Parameters (Sheet Float to Active Delay on T Active to Float Delay off T Input Setup Time to CLK su T Input Hold Time from CLK ...
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PCI and PCI-X Clock Specification Clock measurement conditions are the same for PCI-X devices as for conventional PCI devices in a 3.3V signaling environment except for voltage levels specified in Timings” on page 33. The same spread-spectrum clocking techniques ...
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Bridge — Datasheet 5. Period jitter is the deviation between any single period of the clock cyc(average and the average period of the clock, cyc ...
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Bridge Clock Timings Table 27. 41210 Bridge Clock Timings Symbol CLK100 T period T rise T fall — — T ccjitter — — — — — CLK133 T Average Period period T Rise time across 600 mV rise ...
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Bridge — Datasheet 2. The average period over any 1 us period of time must be greater than the minimum specified period measured at 2.4V for non-host outputs. high measured at 0.4V for ...
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... VCC33 1. Per PCI-X Bus segment 3.7 Power Delivery Guidelines Please refer to the Intel® 41210 Serial to Parallel PCI Bridge Design Guide. 3.8 Reference and Compensation Pins The 41210 Bridge has one reference pin and three compensation pins: • PE_RCOMP[1:0] are two separate pins that provide voltage compensation for the PCI Express interface on the 41210 Bridge. The nominal compensation voltage is 0.5V. An external 24.9 ± ...
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... For TDP specifications, see 41210 Bridge Thermal Specifications for the 41210 Bridge component. FC-BGA packages have poor heat transfer capability into the board and have minimal thermal capability without thermal solutions. Intel recommends that system designers plan for a heatsink when using the 41210 Bridge component. ...
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... Solder-Down Anchor Note: The enabled components may not be currently available from all suppliers. Contact the supplier directly to verify time of component availability. Parameter T case Mode#1/Mode#1 Mode#1/No Connect DDR/No Connect Intel Part Number (Part Number) C76435-001 CCI/ACK C76434-001 CCI/ACK Chomerics A69230-001 69-12-22066-T710 C17725-001 ...
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Bridge — Datasheet Package Specification and Ballout 4.1 Package Specification The 41210 Bridge 567-ball FCBGA package, 31mm X 31mm in size, with a 1.27mm ball pitch (see Figure 9 Figure 9. 41210 Bridge Package Dimensions (Top ...
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Figure 10. 41210 Bridge Package Dimensions (Side View) Note: Primary datum -C- and seating plane are defined by the spherical crowns of the solder balls. Note: All dimensions and tolerances conform to ANSI Y14.5M-1982 Datasheet — 41210 Bridge 41 ...
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Bridge — Datasheet 4.2 Ball Map AD[ REQ64# AD[ ACK64 E2# AD[18 VCC33 AD[17 AD[16 IRDY# ...
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SS SS [15] [12] [10] [7] _ _AD _ _AD VCC33 SS SS PAR [14] C E0# [9] _ _AD _AD _AD _ VCC33 SS C E1# [13] [11] ...
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Bridge — Datasheet 4.3 Signal List, sorted by Ball Location Table 31. Signal List, sorted by Ball Name (Sheet Ball Signal Name A1 A2 B_STRAP5 A3 RESERVED5 A4 VSS A5 NC2 A6 TDO A7 VCC33 A8 ...
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Table 31. Signal List, sorted by Ball Name (Sheet Ball Signal Name G1 B_INTB# G2 VSS G3 B_NC5 G4 B_NC8 G5 VSS G6 B_CBE6# G7 B_CBE7# G8 VSS G9 B_CBE4# G10 PERN[7] G11 VSS G12 PERN[3] G13 ...
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Bridge — Datasheet Table 31. Signal List, sorted by Ball Name (Sheet Ball Signal Name N1 N2 VSS N3 B_AD[37] N4 B_AD[38] N5 VSS N6 B_AD[52] N7 B_AD[53] N8 B_RST# N9 VSS N10 VCC15 N11 VSS ...
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Table 31. Signal List, sorted by Ball Name (Sheet Ball Signal Name W1 B_AD[16] W2 VCC33 W3 B_LOCK# W4 B_TRDY# W5 VSS W6 B_AD[23] W7 B_AD[25] W8 VSS W9 B_AD[29] W10 B_CLKO[0] W11 VCC33 W12 B_GNT4# W13 ...
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Bridge — Datasheet 4.4 Signal List, sorted by Signal Name Table 32. Signal List, sorted by Signal Name (Sheet Ball Signal Name V20 A_133EN AB24 A_ACK64# AC23 A_AD[0] AD23 A_AD[1] AC22 A_AD[2] AB21 A_AD[3] AD21 A_AD[4] ...
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Table 32. Signal List, sorted by Signal Name (Sheet Ball Signal Name AD8 B_AD[10] AB9 B_AD[11] AD9 B_AD[12] AB10 B_AD[13] AC10 B_AD[14] AD11 B_AD[15] W1 B_AD[16] Y2 B_AD[17] AA2 B_AD[18] AA3 B_AD[19] AB3 B_AD[20] Y4 B_AD[21] Y5 ...
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Bridge — Datasheet Table 32. Signal List, sorted by Signal Name (Sheet Ball Signal Name A15 PERN[1] C13 PERN[2] G12 PERN[3] C10 PERN[4] C9 PERN[5] E12 PERN[6] G10 PERN[7] E15 PERP[0] A16 PERP[1] D13 PERP[2] H12 ...
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Table 32. Signal List, sorted by Signal Name (Sheet Ball Signal Name C5 VSS C8 VSS C20 VSS C23 VSS D11 VSS D14 VSS D17 VSS E2 VSS E5 VSS E8 VSS E10 VSS E13 VSS E20 ...
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