NQ41210 S L7JE Intel, NQ41210 S L7JE Datasheet - Page 15

• Manufacturer Part Number: NQ41210 S L7JE
• Manufacturer: Intel

Specifications of NQ41210 S L7JE

• Package Type: FCBGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Not Compliant

2.8
Table 8.
2.9
Table 9.
SMBus Interface
SMBus Interface Pins
Miscellaneous Pins
Miscellaneous Pins
SMBUS[3:1]
SMBUS[5]
SMBCLK
SMBDAT
CFGRST#
Signal
PERST#
RSTIN#
Signal
TCK
TDO
TDI
Total
I/OD
I/OD
I/O
I/O
O
O
I
I
I
I
I
6
Configuration Reset: This signal is asserted low when ever the bridge goes
through a fundemental reset (PERST#, RSTIN#, or PCI Express Reset). This
signal should be used to indicate when the local initialization methods should be
executed.
Refer to the Intel® 41210 Serial to Parallel PCI Bridge Design Guide for more
information.
PCI Express Fundamental Reset: When low, asynchronously resets the
internal logic (including sticky bits).
Reset In: When Asserted, this signal asynchronously resets the internal logic
and asserts X_RST# output for both PCI interfaces. This signal should be pulled
high for adapter card usage.
TAP Clock In: This is the input clock to the JTAG TAP controller. Acceptable
frequency is 0-16MHz
If not utilizing JTAG, this signal can be left as a no connect.
Test Data In: This is the serial data input to the JTAG BSCAN shift register
chain and to the JTAG BSCAN control logic. This is latched in on the rising edge
of TCK.
If not utilizing JTAG, this signal can be left as a no connect.
Test Data Output: This is the serial data output from the JTAG BSCAN logic
If not utilizing JTAG, this signal can be left as a no connect.
SMBus Clock: This signal should be pulled to 3.3V via an 8.2KOhm
resistor.
SMBus Data: This signal should be pulled to 3.3V via an 8.2KOhm
resistor.
SMBus Addressing Straps: These straps set the SMBus Address for
41210 Bridge. The address is determined as indicated below:
Bit 7‘1’
Bit 6‘1’
Bit 5SMBUS[5]
Bit 4‘0’
Bit 3SMBUS[3]
Bit 2SMBUS[2]
Bit 1SMBUS[1]
These signals (bits 5, 3:1) should be pulled up to 3.3V or down to
ground. Sampled at the rising edge of PERST#.
Description
Description
Datasheet — 41210 Bridge
15