P89V51RD2FA NXP Semiconductors, P89V51RD2FA Datasheet - Page 15

• Manufacturer Part Number: P89V51RD2FA
• Description: MCU 8-Bit 89V 80C51 CISC 64KB Flash 5V 44-Pin PLCC Tube
• Manufacturer: NXP Semiconductors

Specifications of P89V51RD2FA

• Program Memory Size: 64 KB
• Package: 44PLCC
• Device Core: 80C51
• Family Name: 89V
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 32
• Interface Type: SPI/UART
• Number Of Timers: 3
• Ram Size: 1 KB
• Program Memory Type: Flash
• Operating Temperature: -40 to 85 °C
• Controller Family/series: 80C51
• No. Of I/o's: 32
• Ram Memory Size: 1KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 5
• Digital Ic Case Style: LCC
• Core Size: 8 Bit
• Embedded Interface Type: UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
P89V51RB2_RC2_RD2_5
Product data sheet
6.2.3 Software reset
6.2.4 Brownout detect reset
to work during initial power up, before the voltage reaches the brownout detection level.
The POF flag in the PCON register is set to indicate an initial power up condition. The
POF flag will remain active until cleared by software.
Following a power-on or external reset the P89V51RB2/RC2/RD2 will force the SWR and
BSEL bits (FCF[1:0]) = 00. This causes the boot block to be mapped into the lower 8 kB of
code memory and the device will execute the ISP code in the boot block and attempt to
autobaud to the host. If the autobaud is successful the device will remain in ISP mode. If,
after approximately 400 ms, the autobaud is unsuccessful the boot block code will check
to see if the SoftICE flag is set (from a previous programming operation). If the SoftICE
flag is set the device will enter SoftICE mode. If the SoftICE flag is cleared, the boot code
will execute a software reset causing the device to execute the user code from block 0
starting at address 0000H. Note that an external reset applied to the RST pin has the
same effect as a power-on reset.
A software reset is executed by changing the SWR bit (FCF.1) from ‘0’ to ‘1’. A software
reset will reset the program counter to address 0000H and force both the SWR and BSEL
bits (FCF[1:0]) = 10. This will result in the lower 8 kB of the user code memory being
mapped into the user code memory space. Thus the user's code will be executed starting
at address 0000H. A software reset will not change WDTC.2 or RAM data. Other SFRs
will be set to their reset values.
The device includes a brownout detection circuit to protect the system from severe supply
voltage fluctuations. The P89V51RB2/RC2/RD2's brownout detection threshold is 2.35 V.
When V
generate a brownout interrupt but the CPU still runs until the supplied voltage returns to
the brownout detection voltage V
cause a processor reset.
Fig 5. Power-on reset circuit
DD
drops below this voltage threshold, the brownout detect triggers the circuit to
Rev. 05 — 12 November 2009
V
DD
10 F
8.2 k
BOD
C 2
. The default operation for a brownout detection is to
C 1
P89V51RB2/RC2/RD2
RST
XTAL2
XTAL1
8-bit microcontrollers with 80C51 core
V
002aaa543
DD
© NXP B.V. 2009. All rights reserved.
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