XC4VLX40-10FFG668I Xilinx Inc, XC4VLX40-10FFG668I Datasheet - Page 33
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XC4VLX40-10FFG668I
Manufacturer Part Number
XC4VLX40-10FFG668I
Description
FPGA Virtex®-4 Family 41472 Cells 90nm (CMOS) Technology 1.2V 668-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VLX40-10FFG668I
Package
668FCBGA
Family Name
Virtex®-4
Device Logic Units
41472
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
448
Ram Bits
1769472
Number Of Logic Elements/cells
41472
Number Of Labs/clbs
4608
Total Ram Bits
1769472
Number Of I /o
448
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
668-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4VLX40-10FFG668I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Block RAM and FIFO Switching Characteristics
Table 40: Block RAM Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
Notes:
1.
2.
3.
4.
5.
Sequential Delays
Setup and Hold Times Before Clock CLK
Maximum Frequency
T
T
T
T
T
T
T
T
F
F
CLK-to-CLK
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is listed,
there is no positive hold time.
T
T
T
Xilinx block RAMs do not have asynchronous inputs on an enabled port address. During the time that a port is enabled, its addresses must be stable
during the specified set-up time. Do not create an asynchronous input on an enabled port address.
RCKO_DORA
RCKO_DOA
RCCK_ADDR
RDCK_DI
RCCK_EN
RCCK_REGCE
RCCK_SSR
RCCK_WE
MAX
MAX
RCKO_DORA
RCKO_DOA
RCKO_DI
Symbol
/
includes both A and B inputs as well as the parity inputs of A and B.
/
T
/
T
/
includes T
T
RCKD_DI
T
includes T
/
RCKC_EN
RCKC_WE
RCKC_SSR
T
/
T
RCKC_ADDR
RCKC_REGCE
RCKO_DOPA
RCKO_DOWA
as well as the B port equivalent timing parameters.
Clock CLK to DOUT output (without output register)
Clock CLK to DOUT output with ECC
(without output register)
Clock CLK to DOUT output (with output register)
Clock CLK to DOUT output with ECC (with output
register)
ADDR inputs
DIN inputs
EN input
CE input of output register
RST input
WEN input
Write first and no change mode
Read first mode
Read first mode
, T
RCKO_DOPAR
(5)
(4)
, and T
Description
RCKO_DOPAW
www.xilinx.com
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
as well as the B port equivalent timing parameters.
(3)
(2)
500.00
500.00
500.00
1.65
3.00
0.72
2.00
0.34
0.26
0.18
0.26
0.41
0.26
0.25
0.26
0.25
0.26
0.59
0.26
-12
Speed Grade
450.45
450.45
450.45
1.83
3.33
0.80
2.20
0.37
0.28
0.20
0.28
0.45
0.28
0.27
0.28
0.27
0.28
0.65
0.28
-11
400.00
400.00
400.00
2.10
3.83
0.92
2.50
0.43
0.33
0.23
0.33
0.52
0.33
0.32
0.33
0.32
0.33
0.75
0.33
-10
ns, Max
ns, Max
ns, Max
ns, Max
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
Units
MHz
MHz
MHz
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