LTC4210-2CS6#PBF Linear Technology, LTC4210-2CS6#PBF Datasheet - Page 11

• Manufacturer Part Number: LTC4210-2CS6#PBF
• Manufacturer: Linear Technology

Specifications of LTC4210-2CS6#PBF

• Linear Misc Type: Positive Low Voltage
• Family Name: LTC4210-2
• Package Type: TSOT-23
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 16.5V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Product Height (mm): 0.9mm
• Product Length (mm): 2.9mm
• Mounting: Surface Mount
• Pin Count: 6
• Lead Free Status / RoHS Status: Compliant

APPLICATIO S I FOR ATIO
Whichever method of compensation is used, board level
short-circuit testing is highly recommended as board
layout can affect transient performance. Beside frequency
compensation, the total gate capacitance C
determines the GATE start-up as in Equation 6. The C
should be kept below 0.15 F at high supply operation as
the capacitive energy ( 0.5 • C
by the LTC4210 internal pull-down transistor. This pre-
vents the internal pull-down transistor from overheating
when the GATE turns off and/or is servoing during current
limiting.
Timer Function
The TIMER pin handles several key functions with an
external capacitor, C
thresholds: COMP1 (0.2V) and COMP2 (1.3V). The four
timing current sources are:
The 100 A is a nonideal current source approximating a
7k resistor below 0.4V.
Initial Timing Cycle
When the card is being inserted into the bus connector, the
long pins mate first which brings up the supply V
point 1 of Figure 3. The LTC4210 is in reset mode as the
ON pin is low. GATE is pulled low and the TIMER pin is
pulled low with a 100 A source. At time point 2, the short
pin makes contact and ON is pulled high. At this instant, a
start-up check requires that the supply voltage be above
UVLO, the ON pin be above 1.3V and the TIMER pin voltage
be less than 0.2V. When these three conditions are ful-
filled, the initial cycle begins and the TIMER pin is pulled
high with 5 A. At time point 3, the TIMER reaches the
COMP2 threshold and the first portion of the initial cycle
5 A pull-up
60 A pull-up
2 A pull-down
100 A pull-down
U
TIMER
U
. There are two comparator
GATE
• V
W
GATE
2
) is discharged
U
GATE
IN
at time
GATE
also
ends. The 100 A current source then pulls down the
TIMER pin until it reaches 0.2V at time point 4. The initial
cycle delay (time point 2 to time point 4) is related to
C
When the initial cycle terminates, a start-up cycle is
activated and the GATE pin ramps high. The TIMER pin
continues to be pulled down towards ground.
Start-Up Cycle Without Current Limit
The GATE is released with a 10 A pull-up at time point 4
of Figure 3. At time point 5, GATE reaches the external
MOSFET threshold V
ramp up. If the R
the GATE ramps at a constant rate of:
where C
TIMER
t
INITIAL
V
V
TIMER
V
GATE
V
V
OUT
V
GATE
ON
IN
by equation:
T
GATE
RESET
>2.5V
MODE
Figure 3. Normal Operating Sequence
272.9 • C
>1.3V
is the total capacitance at the GATE pin.
C
I
1
GATE
GATE
LTC4210-1/LTC4210-2
2
SENSE
INITIAL
CYCLE
5 A
TH
TIMER
3 4 5
and V
current is below the current limit,
START-UP
COMP2
10 A
CYCLE
100 A
COMP1
ms/ F
V
OUT
TH
starts to follow the GATE
6
NORMAL
CYCLE
7
4210 F03
DISCHARGE
BY LOAD
11
421012f
(5)
(6)