AT52BC6402AT-70CU Atmel, AT52BC6402AT-70CU Datasheet - Page 4

• Manufacturer Part Number: AT52BC6402AT-70CU
• Manufacturer: Atmel

Specifications of AT52BC6402AT-70CU

• Operating Supply Voltage (max): 3.1V
• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

4
AT52BC6402A(T)
ERASE: Before a word can be reprogrammed it must be erased. The erased state of
the memory bits is a logical “1”. The entire memory can be erased by using the Chip
Erase command or individual planes or sectors can be erased by using the Plane Erase
or Sector Erase commands.
CHIP ERASE: Chip Erase is a six-bus cycle operation. The automatic erase begins on
the rising edge of the last WE pulse. Chip Erase does not alter the data of the protected
sectors. After the full chip erase the device will return back to the read mode. The hard-
ware reset during Chip Erase will stop the erase but the data will be of unknown state.
Any command during Chip Erase except Erase Suspend will be ignored.
PLANE ERASE: As a alternative to a full chip erase, the device is organized into four
planes that can be individually erased. The plane erase command is a six-bus cycle
operation. The plane whose address is valid at the sixth falling edge of WE will be
erased provided none of the sectors within the plane are protected.
SECTOR ERASE: As an alternative to a full chip erase or a plane erase, the device is
organized into multiple sectors that can be individually erased. The Sector Erase com-
mand is a six-bus cycle operation. The sector whose address is valid at the sixth falling
edge of WE will be erased provided the given sector has not been protected.
WORD PROGRAMMING: The device is programmed on a word-by-word basis. Pro-
gramming is accomplished via the internal device command register and is a four-bus
cycle operation. The programming address and data are latched in the fourth cycle. The
device will automatically generate the required internal programming pulses. Please
note that a “0” cannot be programmed back to a “1”; only erase operations can convert
“0”s to “1”s.
FLEXIBLE SECTOR PROTECTION: The 64-Mbit device offers two sector protection
modes, the Softlock and the Hardlock. The Softlock mode is optimized as sector protec-
tion for sectors whose content changes frequently. The Hardlock protection mode is
recommended for sectors whose content changes infrequently. Once either of these two
modes is enabled, the contents of the selected sector is read-only and cannot be erased
or programmed. Each sector can be independently programmed for either the Softlock
or Hardlock sector protection mode. At power-up and reset, all sectors have their Soft-
lock protection mode enabled.
SOFTLOCK AND UNLOCK: The Softlock protection mode can be disabled by issuing a
two-bus cycle Unlock command to the selected sector. Once a sector is unlocked, its
contents can be erased or programmed. To enable the Softlock protection mode, a six-
bus cycle Softlock command must be issued to the selected sector.
HARDLOCK AND WRITE PROTECT (WP): The Hardlock sector protection mode oper-
ates in conjunction with the Write Protection (WP) pin. The Hardlock sector protection
mode can be enabled by issuing a six-bus cycle Hardlock software command to the
selected sector. The state of the Write Protect pin affects whether the Hardlock protec-
tion mode can be overridden.
• When the WP pin is low and the Hardlock protection mode is enabled, the sector
• When the WP pin is high, the Hardlock protection mode is overridden and the sector
To disable the Hardlock sector protection mode, the chip must be either reset or power
cycled.
cannot be unlocked and the contents of the sector is read-only.
can be unlocked via the Unlock command.
3441B–STKD–11/04