M36W0R6050B0ZAQE STMicroelectronics, M36W0R6050B0ZAQE Datasheet - Page 6

• Manufacturer Part Number: M36W0R6050B0ZAQE
• Manufacturer: STMicroelectronics

Specifications of M36W0R6050B0ZAQE

• Operating Supply Voltage (max): 1.95V
• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

M36W0R6050T0, M36W0R6050B0
SIGNAL DESCRIPTIONS
See
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A20). Addresses
are common inputs for the Flash Memory and
PSRAM components. The Address Inputs select
the cells in the memory array to access during Bus
Read operations. During Bus Write operations
they control the commands sent to the Command
Interface of the Flash memory Program/Erase
Controller, and they select the cells to access In
the PSRAM.
The Flash memory is accessed through the Chip
Enable signal (E
(W
two Chip Enable signals (E1
Write Enable signal (W
Address Input (A21). Address A21 is an input for
the Flash memory component only. The Flash
memory is accessed through the Chip Enable sig-
nal (E
Data Input/Output (DQ0-DQ15). In the Flash
memory the Data I/O output the data stored at the
selected address during a Bus Read operation or
input a command or the data to be programmed
during a Write Bus operation.
In the PSRAM, the Upper Byte Data Inputs/Out-
puts, DQ8-DQ15, carry the data to or from the up-
per part of the selected address during a Write or
Read operation, when Upper Byte Enable (UB
driven Low.
The Lower Byte Data Inputs/Outputs, DQ0-DQ7,
carry the data to or from the lower part of the se-
lected address during a Write or Read operation,
when Lower Byte Enable (LB
Flash Chip Enable (E
puts activate the memory control logics, input buff-
ers, decoders and sense amplifiers. When Chip
Enable is Low, V
vice is in active mode. When Chip Enable is at V
the Flash memory is deselected, the outputs are
high impedance and the power consumption is re-
duced to the standby level.
Flash Output Enable (G
pins control data outputs during Flash memory
Bus Read operations.
Flash Write Enable (W
controls the Bus Write operation of the Flash
memories’ Command Interface. The data and ad-
dress inputs are latched on the rising edge of Chip
Enable or Write Enable whichever occurs first.
Flash Write Protect (WP
input that gives an additional hardware protection
for each block. When Write Protect is Low, V
Lock-Down is enabled and the protection status of
6/17
F
) signal, while the PSRAM is accessed through
Figure 2., Logic Diagram
F
) and through the Write Enable (W
IL
F
) and through the Write Enable
, and Reset is High, V
F
P
). The Chip Enable in-
F
).
). The
F
F
). The Output Enable
). Write Protect is an
P
P
and
) is driven Low.
and E2
Table 1., Signal
Write
P
IH
) and the
F
, the de-
) signal.
A0-A20
Enable
P
) is
IL
IH
,
the Locked-Down blocks cannot be changed.
When Write Protect is at High, V
disabled and the Locked-Down blocks can be
locked or unlocked. (Refer to Lock Status Table in
M58WR064F(T/B) datasheet).
Flash Reset (RP
hardware reset of the memory. When Reset is at
V
high impedance and the current consumption is
reduced to the Reset Supply Current I
Table 6., Flash Memory DC Characteristics - Cur-
rents, for the value of I
are in the Locked state and the Configuration Reg-
ister is reset. When Reset is at V
normal operation. Exiting Reset mode the device
enters Asynchronous Read mode, but a negative
transition of Chip Enable or Latch Enable is re-
quired to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic with-
out any additional circuitry. It can be tied to V
(refer to
tics -
Flash Latch Enable (L
the address bits on its rising edge. The address
latch is transparent when Latch Enable is Low, V
and it is inhibited when Latch Enable is High, V
Latch Enable can be kept Low (also at board level)
when the Latch Enable function is not required or
supported.
Flash Clock (K
the Flash memory to the microcontroller during
synchronous read operations; the address is
latched on a Clock edge (rising or falling, accord-
ing to the configuration settings) when Latch En-
able is at V
Asynchronous Read and in write operations.
Flash Wait (WAIT
nal used during Synchronous Read to indicate
whether the data on the output bus are valid. This
output is high impedance when Flash Chip Enable
is at V
ured to be active during the wait cycle or one clock
cycle in advance. The WAIT
by Output Enable.
PSRAM Chip Enable (E1
(Low), the Chip Enable, E1
ry state machine, address buffers and decoders,
allowing Read and Write operations to be per-
formed. When de-asserted (High), all other pins
are ignored, and the device is put, automatically, in
low-power Standby mode.
PSRAM Chip Enable (E2
E2
when it is driven Low. Deep Power-down mode is
the lowest power mode.
IL
P
, the memory is in Reset mode: the outputs are
, puts the device in Deep Power-down mode
Voltages).
IH
Table 7., Flash Memory DC Characteris-
or Flash Reset is at V
IL
F
. Clock is don't care during
). The Clock input synchronizes
F
). The Reset input provides a
F
). WAIT is a Flash output sig-
DD2
F
). Latch Enable latches
P
P
. After Reset all blocks
P
). When
). The Chip Enable,
, activates the memo-
F
IL
signal is not gated
IH
. It can be config-
IH
, the device is in
, Lock-Down is
DD2
. Refer to
asserted
RPH
IH
IL
,
.