M36W0R5030T7ZAQE Micron Technology Inc, M36W0R5030T7ZAQE Datasheet - Page 10

• Manufacturer Part Number: M36W0R5030T7ZAQE
• Manufacturer: Micron Technology Inc

Specifications of M36W0R5030T7ZAQE

• Operating Supply Voltage (max): 1.95V
• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Signal descriptions
2
2.1
2.2
2.3
2.4
2.5
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Signal descriptions
See
connected to this device.
Address inputs (A0-A21)
Addresses A0-A18 are common inputs for the flash memory and PSRAM components. The
address inputs select the cells in the memory array to access during bus read operations.
During bus write operations they control the commands sent to the command interface of
the flash memory program/erase controller, and they select the cells to access in the
PSRAM.
Addresses A19-A20 (for the M36W0R5030x7), A20 (for the M36W0R5040x7), and A20-A21
(for the M36W0R6040x7) are inputs for the flash memory component only. The flash
memory is accessed through the Chip Enable signals (
(W
Data input/output (DQ0-DQ15)
For the flash memory, the data I/O outputs the data stored at the selected address during a
bus read operation or inputs a command or the data to be programmed during a write bus
operation.
For the PSRAM, the upper byte data inputs/outputs carry the data to or from the upper part
of the selected address during a write or read operation, when upper byte enable (UB
driven Low.
Likewise, the lower byte data inputs/outputs carry the data to or from the lower part of the
selected address during a write or read operation, when Lower Byte Enable (LB
Low.
Flash Chip Enable (E
The Chip Enable inputs activate the memory control logics, input buffers, decoders and
sense amplifiers. When Chip Enable is Low, V
active mode. When Chip Enable is at V
high impedance and the power consumption is reduced to the standby level.
Flash Output Enable (G
The Output Enable pins control data outputs during flash memory bus read operations.
Flash Write Enable (W
The Write Enable controls the bus write operation of the flash memories’ command
interface. The data and address inputs are latched on the rising edge of Chip Enable or
Write Enable, whichever occurs first.
F
) signal.
Figure 1: Logic diagram
and
F
)
F
Table 2: Signal names
)
F
)
IH
the flash memory is deselected, the outputs are
IL
, and Reset is High, V
E
F
for a brief overview of the signals
) and through the Write Enable
IH
, the device is in
M36W0Rx0x0x7
P
) is driven
P
) is