M36W0R5030T7ZAQE Micron Technology Inc, M36W0R5030T7ZAQE Datasheet - Page 11

• Manufacturer Part Number: M36W0R5030T7ZAQE
• Manufacturer: Micron Technology Inc

Specifications of M36W0R5030T7ZAQE

• Operating Supply Voltage (max): 1.95V
• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

M36W0Rx0x0x7
2.6
2.7
2.8
2.9
2.10
2.11
Flash Write Protect (WP
Write Protect is an input that gives an additional hardware protection for each block. When
Write Protect is Low, V
blocks cannot be changed. When Write Protect is at High, V
the locked-down blocks can be locked or unlocked (refer to the lock status table in
M58WR032KT/B and M58WR064KT/B datasheet).
Flash Reset (RP
The Reset input provides a hardware reset of the memory. When Reset is at V
memory is in reset mode: the outputs are high impedance and the current consumption is
reduced to the Reset supply current I
datasheet for the value of IDD2. After Reset all blocks are in the locked state and the
configuration register is reset. When Reset is at V
exiting reset mode the device enters asynchronous read mode, but a negative transition of
Chip Enable or Latch Enable is required to ensure valid data outputs.
The Reset pin can be interfaced with 3 V logic without any additional circuitry. It can be tied
to V
Flash Latch Enable (L
Latch Enable latches the address bits on its rising edge. The address latch is transparent
when Latch Enable is Low, V
Enable can be kept Low (also at board level) when the Latch Enable function is not required
or supported.
Flash Clock (K
The Clock input synchronizes the flash memory to the microcontroller during synchronous
read operations; the address is latched on a Clock edge (rising or falling, according to the
configuration settings) when Latch Enable is at V
asynchronous read and in write operations.
Flash Wait (WAIT
WAIT is a flash output signal used during synchronous read to indicate whether the data on
the output bus are valid. This output is high impedance when flash Chip Enable is at V
flash Reset is at V
cycle in advance. The WAIT
PSRAM Chip Enable (E
When asserted (Low), the Chip Enable, E
buffers and decoders, allowing read and write operations to be performed. When de-
asserted (High), all other pins are ignored and the device is automatically put in low-power
standby mode.
RPH
(refer to the M58WR032KT/B or M58WR064KT/B datasheet).
IL
. It can be configured to be active during the wait cycle or one clock
F
IL
)
, lock-down is enabled and the protection status of the locked-down
F
F
)
)
F
IL
signal is not gated by Output Enable.
, and it is inhibited when Latch Enable is High, V
F
)
P
F
)
DD2
)
. Refer to the M58WR032KT/B or M58WR064KT/B
P,
activates the memory state machine, address
IL
IH
. Clock is ‘don't care’ during
, the device is in normal operation. Upon
IH
, lock-down is disabled and
Signal descriptions
IL
IH
, the
. Latch
IH
11/24
or