MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 23

• Manufacturer Part Number: MT41J256M8HX-15E:D
• Description: MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-15E:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Compliant

Table 5: 96-Ball FBGA – x16 Ball Descriptions
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
A0, A1, A2, A3, A4,
A5, A6, A7, A8, A9,
A10/AP, A11, A12/
RAS#, CAS#, WE#
BC#, A13
Symbol
CK, CK#
BA[2:0]
RESET#
LDM
ODT
CKE
CS#
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Description
Address inputs: Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one
location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one bank (A10
LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also pro-
vide the op-code during a LOAD MODE command. Address inputs are referenced to
V
and WRITE commands to determine whether burst chop (on-the-fly) will be performed
(HIGH = BL8 or no burst chop, LOW = BC4). See Table 69 (page 112).
Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE,
or PRECHARGE command is being applied. BA[2:0] define which mode
register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0]
are referenced to V
Clock: CK and CK# are differential clock inputs. All control and address input signals
are sampled on the crossing of the positive edge of CK and the negative edge of CK#.
Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is de-
pendent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW
provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle),or
active power-down (row active in any bank). CKE is synchronous for
power-down entry and exit and for self refresh entry. CKE is asynchronous for self re-
fresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during
POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF RE-
FRESH. CKE is referenced to V
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the com-
mand decoder. All commands are masked when CS# is registered HIGH. CS#
provides for external rank selection on systems with multiple ranks. CS# is considered
part of the command code. CS# is referenced to V
Input data mask: LDM is a lower-byte, input mask signal for write data. Lower-byte
input data is masked when LDM is sampled HIGH along with the input data during a
write access. Although the LDM ball is input-only, the LDM loading is designed to
match that of the DQ and DQS balls. LDM is referenced to V
On-die termination: ODT enables (registered HIGH) and disables (registered LOW) ter-
mination resistance internal to the DDR3 SDRAM. When enabled in normal
operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS, LDQS#,
UDQS, UDQS#, LDM, and UDM for the x16; DQ0[7:0], DQS, DQS#, DM/TDQS, and NF/
TDQS# (when TDQS is enabled) for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The
ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to
V
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command
being entered and are referenced to V
Reset: RESET# is an active LOW CMOS input referenced to V
er is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × V
LOW ≤ 0.2 × V
REFCA
REFCA
. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ
.
DDQ
. RESET# assertion and desertion are asynchronous.
REFCA
.
23
REFCA
.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Ball Assignments and Descriptions
REFCA
.
2Gb: x4, x8, x16 DDR3 SDRAM
REFCA
.
REFDQ
© 2006 Micron Technology, Inc. All rights reserved.
SS
. The RESET# input receiv-
.
DD
and DC