K4D263238KVC50 Samsung Semiconductor, K4D263238KVC50 Datasheet - Page 15

• Manufacturer Part Number: K4D263238KVC50
• Manufacturer: Samsung Semiconductor
• Type: FPMr

Specifications of K4D263238KVC50

• Organization: 4Mx32
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 700ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.625V
• Operating Supply Voltage (min): 2.375V
• Supply Current: 60mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

K4D263238K
AC CHARACTERISTICS (I)
Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM
AC CHARACTERISTICS (II)
* 200/166MHz are supported in K4D263238K-VC40
* 166MHz is supported in K4D263238K-VC50
K4D263238K-VC40
K4D263238K-VC50
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay for Read
RAS to CAS delay for Write
Row precharge time
Row active to Row active
Last data in to Row precharge
Last data in to Row precharge
@Auto Precharge
Auto precharge write recovery + Pre-
charge
Last data in to Read command
Col. address to Col. address
Mode register set cycle time
Exit self refresh to read command
Power down exit time
Refresh interval time
250MHz ( 4.0ns )
200MHz ( 5.0ns )
166MHz ( 6.0ns )
200MHz ( 5.0ns )
166MHz ( 6.0ns )
Frequency
Frequency
2. The number of clock of tRP is restricted by the number of clock of tRAS and tRP
3. The number of clock of tWR_A is fixed. It can’t be changed by tCK
4. tRCDWR is equal to tRCDRD-2tCK and the number of clock can not be lower than 2tCK.
5. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer unconditionally.
Parameter
Cas Latency
Cas Latency
3
3
3
3
3
tRC
tRC
12
10
10
tRC
tRFC
tRAS
tRCDRD
tRCDWR
tRP
tRRD
tWR
tWR_A
tDAL
tCDLR
tCCD
tMRD
tXSR
tPDEX
tREF
9
9
Symbol
tRFC
tRFC
14
11
11
9
9
3tCK+tIS
Min
200
48
56
32
16
16
10
15
8
3
7
2
1
2
-
tRAS
tRAS
8
7
6
7
6
- 15/19 -
-40
tRCDRD tRCDWR
tRCDRD tRCDWR
100K
Max
7.8
4
3
3
3
3
-
-
-
-
-
-
-
-
-
-
-
-
-
2
2
2
2
2
3tCK+tIS
Min
200
50
55
35
15
10
15
10
15
3
6
2
1
2
-
128M GDDR SDRAM
tRP
tRP
4
3
3
3
3
-50
Rev. 1.2 October 2007
100K
Max
tRRD
tRRD
7.8
-
-
-
-
-
-
-
-
-
-
-
-
-
3
2
2
2
2
tDAL
tDAL
Unit
tCK
tCK
tCK
tCK
tCK
tCK
7
6
6
6
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
Note
Unit
tCK
tCK
tCK
Unit
tCK
tCK
2,5
3,5
5
5
5
5
4
5
5
3
1