K4D263238KVC50 Samsung Semiconductor, K4D263238KVC50 Datasheet - Page 7

• Manufacturer Part Number: K4D263238KVC50
• Manufacturer: Samsung Semiconductor
• Type: FPMr

Specifications of K4D263238KVC50

• Organization: 4Mx32
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 700ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.625V
• Operating Supply Voltage (min): 2.375V
• Supply Current: 60mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

K4D263238K
FUNCTIONAL DESCRIPTION
• Power-Up Sequence
DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
* When the operating frequency is changed, DLL reset should be required again.
Command
After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL.
*1
*
Power up & Initialization Sequence
1,2
stable for 200us
7. Issue precharge command for all banks of the device.
6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.
1. Apply power and keep CKE at low state (All other inputs may be undefined)
2. Start clock and maintain stable condition for minimum 200us.
3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high.
4. Issue precharge command for all banks of the device.
5. Issue a EMRS command to enable DLL
8. Issue at least 2 or more auto-refresh commands.
9. Issue a mode register set command with A8 to low to initialize the mode register.
Inputs must be
*1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6&7 is regardless of the order.
CK
CK
- Apply VDD before
- Apply VDDQ before
- The VDD voltage ramp time must be no greater than 200 ms from when VDD ramps
from 300 mV to VDD min and the power voltage ramps are without any slope reversal.
0
ALL Banks
precharge
1
2
t
RP
3
or with
EMRS
or with
4
2 Clock min.
VDDQ .
VREF & VTT
5
DLL Reset
MRS
6
2 Clock min.
7
ALL Banks
precharge
8
- 7/19 -
9
tRP
10
1st Auto
Refresh
200 Clock min.
11
t
12
RFC
13
2nd Auto
Refresh
128M GDDR SDRAM
14
Rev. 1.2 October 2007
15
t
RFC
16
17
Register Set
Mode
18
2 Clock min.
19
Command
Any