IS45S16100C1-7TA1 ISSI, Integrated Silicon Solution Inc, IS45S16100C1-7TA1 Datasheet - Page 28

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IS45S16100C1-7TA1

Manufacturer Part Number
IS45S16100C1-7TA1
Description
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Datasheet

Specifications of IS45S16100C1-7TA1

Organization
1Mx16
Density
16Mb
Address Bus
12b
Access Time (max)
6/5.5ns
Maximum Clock Rate
143MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
150mA
Pin Count
50
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Not Compliant
28
IS45S16100C1
Interval Between Read Command
A new command can be executed while a read cycle is in
progress, i.e., before that cycle completes. When the
second read command is executed, after the CAS latency
has elapsed, data corresponding to the new read command
is output in place of the data due to the previous read
command.
CAS latency = 2, burstlength = 4
Interval Between Write Command
A new command can be executed while a write cycle is in
progress, i.e., before that cycle completes. At the point the
second write command is executed, data corresponding to
the new write command can be input in place of the data
for the previous write command.
CAS latency = 3, burstlength = 4
COMMAND
COMMAND
CLK
DQ
CLK
DQ
READ (CA=A, BANK 0) READ (CA=B, BANK 0)
WRITE (CA=A, BANK 0) WRITE (CA=B, BANK 0)
READ A0
WRITE A0 WRITE B0
D
IN
A0
READ B0
t
CCD
D
IN
t
CCD
B0
Integrated Silicon Solution, Inc. — www.issi.com —
D
OUT
D
A0
IN
B1
D
OUT
The interval between two write commands (t
at least one clock cycle.
The selected bank must be set to the active state before
executing this command.
The interval between two read command (t
least one clock cycle.
The selected bank must be set to the active state before
executing this command.
D
B0
IN
B2
D
OUT
D
B1
IN
B3
D
OUT
B2
D
OUT
B3
ISSI
1-800-379-4774
CCD
CCD
) must be at
) must be
01/03/06
Rev. C
®

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