5962-8751512LA QP SEMICONDUCTOR, 5962-8751512LA Datasheet - Page 10
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5962-8751512LA
Manufacturer Part Number
5962-8751512LA
Description
Manufacturer
QP SEMICONDUCTOR
Datasheet
1.5962-8751512LA.pdf
(16 pages)
Specifications of 5962-8751512LA
Organization
8Kx8
Interface Type
Parallel
In System Programmable
In System/External
Frequency (max)
Not RequiredMHz
Access Time (max)
25ns
Package Type
CDIP
Reprogramming Technique
UV
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Pin Count
24
Mounting
Through Hole
Operating Temp Range
-55C to 125C
Operating Temperature Classification
Military
Lead Free Status / RoHS Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
DSCC FORM 2234
APR 97
883 including groups A, B, C, and D inspections. The following additional criteria shall apply.
4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD-
4.3.1 Group A inspection.
Margin test method B.
DEFENSE SUPPLY CENTER COLUMBUS
c.
d.
a. Tests shall be as specified in table II herein.
b. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted.
(10)
(11)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(1)
(2)
(3)
(4)
(4a) Steps 1 through 4 may be performed at the wafer level. The maximum storage temperature shall not exceed
(5)
(6)
(7)
(8)
(9)
All devices selected for testing shall be programmed with a checkerboard pattern or equivalent. After completion of all
testing, the devices shall be erased and verified except devices being submitted to groups B, C, and D testing.
As a minimum, subgroups 7 and 8 shall consist of verifying the EPROM pattern specified.
COLUMBUS, OHIO 43218-3990
MICROCIRCUIT DRAWING
Bake, unbiased, for 72 hours at +140°C or for 48 hours at +150°C or for 8 hours at +200°C or 48 hours at 225°C
(unassembled devices only).
At +25°C, perform a margin test using V
Perform dynamic burn-in in accordance with 4.2a.
At +25°C, perform a margin test using V
Perform electrical test in accordance with 4.2b.
Erase in accordance with 3.6.1. Devices may be submitted to quality conformance inspection.
Verify erasure in accordance with 3.6.3.
Program at +25°C greater than 95 percent of the bit locations, including the slowest programming cell. The
remaining cells shall provide a worst case speed pattern.
Bake, unbiased, for 72 hours at +140°C or for 48 hours at +150°C or for 8 hours at +200°C or for 2 hours at
+300°C for unassembled devices only.
Perform margin test using V
Erase (see 3.6.1).
+200°C for packaged devices or +300°C for unassembled devices.
Program at +25°C with a 50 percent pattern (checkerboard or equivalent).
Perform margin test using V
Perform dynamic burn-in in accordance with 4.2a.
Perform margin test using V
Perform electrical tests (see 4.2b).
Erase (see 3.6.1), except devices submitted for groups A, B, C, and D testing.
Verify erasure (see 3.6.3).
STANDARD
m
m
m
= +5.55 V and V
= +5.75 V and V
= +5.55 V and V
m
m
= +5.8 V to loose timing (i.e., t
= +5.8 V.
m
m
m
= +4.40 V at +25°C using loose timing (i.e., t
= +4.40 V at +25°C with loose timing.
= +4.40 V at +25°C using loose timing.
SIZE
A
REVISION LEVEL
ACC
= 1 µs).
B
ACC
SHEET
= 1 µs).
5962-87515
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