CY7C4245V-25ASC Cypress Semiconductor Corp, CY7C4245V-25ASC Datasheet
CY7C4245V-25ASC
Specifications of CY7C4245V-25ASC
Related parts for CY7C4245V-25ASC
CY7C4245V-25ASC Summary of contents
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... High-speed, low-power, first-in first-out (FIFO) ■ memories 512 x 18 (CY7C4215V) ❐ (CY7C4225V) ❐ (CY7C4235V) ❐ (CY7C4245V) ❐ 0.65µ CMOS ■ High-speed 67-MHz operation (15-ns read/write cycle times) ■ Low power ■ ❐ CC ...
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Logic Block Diagram Document #: 38-06029 Rev. *D CY7C4225V/4215V CY7C4235V/4245V Page [+] Feedback [+] Feedback ...
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Contents Features............................................................................. 1 Functional Description..................................................... 1 Logic Block Diagram........................................................ 2 Contents ............................................................................ 3 Pin Configuration ............................................................. 4 Selection Guide ................................................................ 4 Pin Definitions .................................................................. 5 Architecture ...................................................................... 6 Resetting the FIFO............................................................ 6 FIFO Operation ................................................................. 6 Programming .................................................................... 6 Flag ...
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... STQFP Document #: 38-06029 Rev. *D Figure 1. 64-Pin STQFP/TQFP Top View CY7C4215V 41 8 CY7C4225V CY7C4235V 38 11 CY7C4245V CY7C42X5V-15 CY7C42X5V-25 66 CY7C4235V CY7C4245V 64-pin 14x14 TQFP 64-pin 14x14 TQFP 64-pin 10x10 64-pin 10x10 STQFP STQFP CY7C4225V/4215V CY7C4235V/4245V GND GND GND CY7C42X5V-35 Unit 28.6 MHz Page ...
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Pin Definitions Signal Name Description I/O D Data Inputs I 0−17 Q Data Outputs O Data outputs for an 18-bit bus. 0−17 WEN Write Enable I REN Read Enable I WCLK Write Clock I RCLK Read Clock I WXO/HF Write ...
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Architecture The CY7C42X5V consists of an array words of 18 bits each (implemented by a dual-port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, REN, WEN, RS), and flags (EF, ...
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Flag Operation The CY7C42X5V devices provide five flag pins to indicate the condition of the FIFO contents. Empty and Full are synchronous. PAE and PAF are synchronous if V /SMODE is tied Full Flag The Full Flag ...
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Width Expansion Configuration The CY7C42X5V can be expanded in width to provide word widths greater than 18 in increments of 18. During width expansion mode all control line inputs are common and all flags are available. Empty (Full) flags should ...
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Figure 3. Block Diagram of Low-Voltage Synchronous FIFO Memory with Programmable Flags used in Depth Expansion Configuration FIRSTLOAD (FL) DATAIN (D) FIRSTLOAD (FL) WRITECLOCK (WCLK) WRITE ENABLE (WEN) RESET(RS) LOAD (LD) FF PAF FIRSTLOAD (FL) Document #: 38-06029 Rev. *D ...
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Maximum Ratings [4] (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................... −65 Ambient Temperature with Power Applied................................................ −55 Supply Voltage to Ground Potential .................−0.5V to +5.0V DC Voltage Applied to Outputs in ...
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Figure 4. AC Test Loads and Waveforms R1 = 330Ω 3.3V OUTPUT C L INCLUDING JIG AND SCOPE Equivalent to: THÉVENIN EQUIVALENT Rth = 200Ω OUTPUT Switching Characteristics Over the Operating Range Parameter Description t Clock Cycle Frequency S t ...
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Switching Characteristics Over the Operating Range (continued) Parameter Description t Clock to Expansion Out XO t Expansion in Pulse Width XI t Expansion in Set-up Time XIS t Skew Time between Read Clock and Write Clock for SKEW1 Full Flag ...
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Switching Waveforms (continued) t RCLK t t ENS ENH REN EF Q – OLZ OE WCLK WEN RS REN, WEN, LD EF,PAE FF,PAF – Notes 15 the minimum time between a ...
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Switching Waveforms (continued) Figure 8. First Data Word Latency after Reset with Simultaneous Read and Write WCLK –D D (FIRSTVALID WRITE ENS WEN t SKEW2 RCLK EF REN Q – ...
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Switching Waveforms (continued) NO WRITE WCLK t [14] SKEW1 D – WFF FF WEN RCLK t ENS REN LOW OE Q –q DATA IN OUTPUT REGISTER CLKH WCLK WEN HF HALF FULL OR LESS ...
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Switching Waveforms (continued) Figure 12. Programmable Almost Empty Flag Timing t CLKH WCLK WEN [20] PAE RCLK REN Figure 13. Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW) t CLKH WCLK WEN PAE t SKEW3 RCLK ...
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... CY7C4215V. 1024 – m words in CY7C4225V, 2048 − m words in CY7C4235V, and 4096 – m words in CY7C4245V. 27. 256 − words in CY7C4205V, 512 − words in CY7C4215V, 1024 − CY7C4225V, 2048 − CY74235V, and 4096 − words in CY7C4245V. 28 write is performed on this rising edge of the write clock, there will be Full – (m–1) words of the FIFO when PAF goes LOW. ...
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Switching Waveforms (continued) t CLK t CLKH WCLK t ENS LD t ENS WEN – CLK t CLKH RCLK t ENS LD t ENS REN Q – CLKH WCLK WXO t ...
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Switching Waveforms (continued) t CLKH RCLK RXO t ENS REN WXI WCLK RXI RCLK FL/RT REN/WEN EF/FF and/all async flags HF/PAE/PAF Notes 32. Read from Last Physical Location. 33. Clocks are free running in this case. 34. The flags may ...
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... Low-Voltage Synchronous FIFO 15 CY7C4225V-15ASXC Low-Voltage Synchronous FIFO 15 CY7C4235V-15ASC CY7C4235V-15ASXC Low-Voltage Synchronous FIFO 15 CY7C4245V-15ASXC 25 CY7C4245V-25ASC Document #: 38-06029 Rev. *D Package Package Name Type A64 64-Pin Pb-Free 10x10 Thin Quad Flatpack A64 64-Pin Pb-Free 10x10 Thin Quad Flatpack A64 64-Pin 10x10 Thin Quad Flatpack ...
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Package Diagrams Document #: 38-06029 Rev. *D Figure 23. 64-Pin TQFP (10X10X1.4 mm) CY7C4225V/4215V CY7C4235V/4245V 51-85051 *B Page [+] Feedback [+] Feedback ...
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Document #: 38-06029 Rev. *D Figure 24. 64-Pin TQFP (14X14X1.4 mm) CY7C4225V/4215V CY7C4235V/4245V 51-85046 *D Page [+] Feedback [+] Feedback ...
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... Page 12: WEN changed to REN (typo) Page 13: WCLK changed to RCLK (typo) YIM Added Pb-Free Logo Added Pb-Free parts to ordering information: CY7C4205V-15ASXC, CY7C4215V-15ASXC, CY7C4225V-15ASXC, CY7C4235V-15ASXC, CY7C4245V-15ASXC, CY7C4245V-25ASXC RAME Added Contents Updated package diagrams Removed inactive parts from Ordering information table Updated links in Sales, Solutions and Legal Information cypress ...