M25P32-VMW3TGB NUMONYX, M25P32-VMW3TGB Datasheet - Page 15

• Manufacturer Part Number: M25P32-VMW3TGB
• Manufacturer: NUMONYX

Specifications of M25P32-VMW3TGB

• Cell Type: NOR
• Density: 32Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 125C
• Package Type: SO W
• Sync/async: Synchronous
• Operating Temperature Classification: Automotive
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 4M
• Supply Current: 8mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Supplier Unconfirmed

4.7
Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25P32 features the following data protection mechanisms:
Table 2.
1. The device is ready to accept a Bulk Erase instruction only if, all Block Protect (BP2, BP1, BP0) are 0.
BP2
Status Register
bit
0
0
0
0
1
1
1
1
Power On Reset and an internal timer (t
inadvertent changes while the power supply is outside the operating specification.
Program, Erase and Write Status Register instructions are checked that they consist of
a number of clock pulses that is a multiple of eight, before they are accepted for
execution.
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
–
–
–
–
–
The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as
read-only. This is the Software Protected Mode (SPM).
The Write Protect (W/V
Status Register Write Disable (SRWD) bit to be protected. This is the Hardware
Protected Mode (HPM).
In addition to the low power consumption feature, the Deep Power-down mode offers
extra software protection, as all Write, Program and Erase instructions are ignored.
content
BP1
bit
0
0
1
1
0
0
1
1
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Page Program (PP) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
BP0
Protected area sizes
bit
1
1
0
0
1
0
0
1
none
Upper 64th (Sector 63)
Upper 32nd (two sectors: 62 and 63) Lower 31/32nds (62 sectors: 0 to 61)
Upper sixteenth (four sectors: 60 to
63)
Upper eighth (eight sectors: 56 to 63) Lower seven-eighths (56 sectors: 0 to 55)
Upper quarter (sixteen sectors: 48 to
63)
Upper half (thirty-two sectors: 32 to
63)
All sectors (64 sectors: 0 to 63)
Protected area
PP
) signal allows the Block Protect (BP2, BP1, BP0) bits and
PUW
Memory content
) can provide protection against
All sectors
Lower 63/64ths (63 sectors: 0 to 62)
Lower 15/16ths (60 sectors: 0 to 59)
Lower three-quarters (48 sectors: 0 to 47)
Lower half (32 sectors: 0 to 31)
none
(1)
Unprotected area
(64 sectors: 0 to 63)
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