MT29F2G08ABBEAHC:E Micron Technology Inc, MT29F2G08ABBEAHC:E Datasheet - Page 20

• Manufacturer Part Number: MT29F2G08ABBEAHC:E
• Manufacturer: Micron Technology Inc

Specifications of MT29F2G08ABBEAHC:E

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Asynchronous Addresses
Figure 12: Asynchronous Address Latch Cycle
PDF: 09005aef83b83f42
m69a_2gb_nand.pdf – Rev. H 09/10 EN
WE#
ALE
I/Ox
CLE
CE#
An asynchronous address is written from I/O[7:0] to the address register on the rising
edge of WE# when CE# is LOW, ALE is HIGH, CLE is LOW, and RE# is HIGH.
Bits that are not part of the address space must be LOW (see Device and Array Organiza-
tion). The number of cycles required for each command varies. Refer to the command
descriptions to determine addressing requirements.
Addresses are typically ignored by die (LUNs) that are busy (RDY = 0); however, some
addresses are accepted by die (LUNs) even when they are busy; for example, like ad-
dress cycles that follow the READ STATUS ENHANCED (78h) command.
t CS
t CLS
t WP
t ALS
t DS
add 1
Col
t WC
t DH
t ALH
t WH
add 2
Col
20
Asynchronous Interface Bus Operation
add 1
Row
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2Gb: x8, x16 NAND Flash Memory
add 2
Row
Don’t Care
© 2009 Micron Technology, Inc. All rights reserved.
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Row
Undefined