AM29LV010B-70JI Spansion Inc., AM29LV010B-70JI Datasheet - Page 18
![no-image](/images/manufacturer_photos/0/6/621/spansion_inc__sml.jpg)
AM29LV010B-70JI
Manufacturer Part Number
AM29LV010B-70JI
Description
Manufacturer
Spansion Inc.
Datasheet
1.AM29LV010B-70JI.pdf
(37 pages)
Specifications of AM29LV010B-70JI
Cell Type
NOR
Density
1Mb
Access Time (max)
70ns
Interface Type
Parallel
Boot Type
Not Required
Address Bus
17b
Operating Supply Voltage (typ)
3/3.3V
Operating Temp Range
-40C to 85C
Package Type
PLCC
Program/erase Volt (typ)
2.7 to 3.6V
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
128K
Supply Current
12mA
Mounting
Surface Mount
Pin Count
32
Lead Free Status / RoHS Status
Not Compliant
WRITE OPERATION STATUS
The device provides several bits to determine the
status of a write operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 5 and the following subsections describe
the functions of these bits. DQ7, and DQ6 each offer a
method for determining whether a program or erase
operation is complete or in progress. These three bits
are discussed first.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host
system whether an Embedded Algorithm is in progress
or completed, or whether the device is in Erase Sus-
pend. Data# Polling is valid after the rising edge of the
final WE# pulse in the program or erase command
sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then the device returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status
information on DQ7.
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data#
Polling on DQ7 is active for approximately 100 µs, then
the device returns to reading array data. If not all
selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores
the selected sectors that are protected.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7–
DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. Figure 14, Data#
Polling Timings (During Embedded Algorithms), in the
“AC Characteristics” section illustrates this.
18
D A T A S H E E T
Am29LV010B
Table 5 shows the outputs for Data# Polling on DQ7.
Figure 3 shows the Data# Polling algorithm.
Notes:
1. VA = Valid address for programming. During a sector
2. DQ7 should be rechecked even if DQ5 = “1” because
No
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
DQ7 may change simultaneously with DQ5.
Figure 3. Data# Polling Algorithm
Read DQ7–DQ0
Read DQ7–DQ0
DQ7 = Data?
DQ7 = Data?
Addr = VA
Addr = VA
DQ5 = 1?
START
FAIL
No
Yes
No
22140D7 February 24, 2009
Yes
Yes
PASS