THNCF256MAA Toshiba, THNCF256MAA Datasheet - Page 16

• Manufacturer Part Number: THNCF256MAA
• Manufacturer: Toshiba
• Type: CompactFlashr

Specifications of THNCF256MAA

• Density: 256MByte
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature (min): 0C
• Operating Temperature (max): 60C
• Package Type: Not Required
• Mounting: Socket
• Pin Count: 50
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.97/4.5V
• Operating Supply Voltage (max): 3.63/5.5V
• Programmable: Yes
• Lead Free Status / RoHS Status: Supplier Unconfirmed

True IDE Mode
True IDE Mode
True IDE Mode
True IDE Mode
The card can be configured in a True IDE This card is configured in this mode only when the-OE input signal is
asserted GND by the host. In this True IDE mode Attribute Registers are not accessible from the host. Only
I/O operation to the task file and data register is allowed. If this card is configured during power on sequence,
data register is accessed in word (16-bit). The card permits 8-bit accessed if the user issues a Set Feature
Command to put the device in 8-bit mode.
True I
True I
True I
True IDE Mode Read I/O Function
Mode
Mode
Mode
Mode
Invalid mode
Standby mode
Data register access
Alternate status access
Other task file access
Note: x: L or H
True IDE Mode Write I/O Function
True IDE Mode Write I/O Function
True IDE Mode Write I/O Function
True IDE Mode Write I/O Function
Mode
Mode
Mode
Mode
Invalid mode
Standby mode
Data register access
Control register access
Other task file access
Note: x: L or H
True IDE Mode I/O Access Timing Example
True IDE Mode I/O Access Timing Example
True IDE Mode I/O Access Timing Example
True IDE Mode I/O Access Timing Example
D0 to D15
DE Mode Read I/O Function
DE Mode Read I/O Function
DE Mode Read I/O Function
-IOWR
A0 to A2
-IOIS16
-IORD
-CE
read cycle
- - - - CE2
- - - - CE2
CE2
CE2
CE2
CE2
CE2
CE2
H
H
H
H
H
H
L
L
L
L
- - - - CE1
- - - - CE1
Dout
CE1
CE1
CE1
CE1
CE1
CE1
H
H
H
H
L
L
L
L
L
L
A0 to A2
A0 to A2
A0 to A2
A0 to A2
A0 to A2
A0 to A2
A0 to A2
A0 to A2
1-7H
1-7H
6H
6H
x
x
0
x
x
0
- - - - IORD
- - - - IORD
IORD
IORD
IORD
IORD
IORD
IORD
L
H
H
H
x
x
L
L
x
x
- - - - OWR
- - - - OWR
OWR
OWR
OWR
OWR
OWR
OWR
H
H
H
L
L
L
x
x
x
x
write cycle
write cycle
write cycle
write cycle
THNCFxxxMAA Series
Preliminary version
D8 to D15
D8 to D15
High-Z
High-Z
odd byte
High-Z
High-Z
D8 to D15
D8 to D15
don’t care
don’t care
odd byte
don’t care
don’t care
D8 to D15
D8 to D15
D8 to D15
D8 to D15
Din
2001-09-05 16/52
D0 to D7
D0 to D7
High-Z
High-Z
even byte
status out
data
D0 to D7
D0 to D7
don’t care
don’t care
even byte
control in
data
D0 to D7
D0 to D7
D0 to D7
D0 to D7