SMC256BFJ6E Micron Technology Inc, SMC256BFJ6E Datasheet - Page 48

• Manufacturer Part Number: SMC256BFJ6E
• Manufacturer: Micron Technology Inc

Specifications of SMC256BFJ6E

• Lead Free Status / RoHS Status: Supplier Unconfirmed

CF-ATA registers
Table 42.
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
9.2.8
48/90
PIO byte data register (selected using
Set Features command)
DMA word data register
PIO word data register
Data register
Data register access
Error register
The error register is a read-only register, located at address 1F1h [171h], offset 1h, 0Dh.
This read only register contains additional information about the source of an error when an
error is indicated in bit 0 of the status register. The bits are defined in
is accessed on data bits D15 to D8 during a write operation to offset 0 with –CE2 Low and –
CE1 High.
Bit 7 (BBK)
This bit is set when a bad block is detected.
Bit 6 (UNC)
This bit is set when an uncorrectable error is encountered.
Bit 5
This bit is ‘0’.
Bit 4 (IDNF)
This bit is set if the requested sector ID is in error or cannot be found.
Bit 3
This bit is ‘0’.
Bit 2 (abort)
This bit is set if the command has been aborted because of a card status condition (not
ready, write fault, etc.) or when an invalid command has been issued.
Bit 1
This bit is ‘0’.
Bit 0 (AMNF)
This bit is set when there is a general error.
(True IDE mode)
–CS1
1
1
1
–CS0
0
1
0
A0
X
0
0
-DMACK
1
0
1
Offset
Table
0h
0h
X
43. This register
D15 to D0
D15 to D0
SMCxxxBF
Data bus
D7 to D0