IS66WVE2M16BLL-70BLI ISSI, Integrated Silicon Solution Inc, IS66WVE2M16BLL-70BLI Datasheet
IS66WVE2M16BLL-70BLI
Specifications of IS66WVE2M16BLL-70BLI
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IS66WVE2M16BLL-70BLI Summary of contents
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... Core Async/Page PSRAM Overview The IS66WVE2M16BLL is an integrated memory device containing 32Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 2M words by 16 bits. The device includes several power saving modes : Partial Array Refresh mode where data is retained in a portion of the array and Deep Power Down mode ...
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... The system-configurable refresh mechanisms are accessed through the CR. A0~A20 CE# WE# Control OE# Logic LB# UB# ZZ# Rev.00C | March 2010 Address Decode Logic 2048K X 16 Memory Array Configuration Register (CR) [ Functional Block Diagram] www.issi.com - SRAM@issi.com IS66WVE2M16BLL Advanced Information Input /Output DRAM Mux And Buffers DQ0~DQ15 2 ...
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... A0 A1 DQ8 UB DQ9 DQ10 A5 A6 VSSQ DQ11 A17 A7 DQ12 NC A16 DQ13 A14 A15 A19 A12 A13 A10 A18 A8 A9 [Top View] (Ball Down) www.issi.com - SRAM@issi.com IS66WVE2M16BLL Advanced Information ZZ# CE# DQ0 DQ1 DQ2 DQ3 VDD DQ4 VSS DQ5 DQ6 WE# DQ7 A11 A20 3 ...
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... DQ2 4 VSSQ 5 OE# 6 VDDQ 7 DQ9 8 DQ1 9 DQ8 10 DQ0 A10 14 A11 15 UB# 16 A17 17 A18 18 A19 19 CE Rev.00C | March 2010 www.issi.com - SRAM@issi.com IS66WVE2M16BLL Advanced Information 48 DQ4 47 DQ12 46 ZZ# 45 DQ5 44 DQ13 43 DQ6 42 DQ14 41 DQ7 40 DQ15 39 VSS 38 VDD 37 A16 36 A15 35 A14 34 A13 33 A12 32 LB A20 ...
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... All VSSQ supply pins must be connected to Ground Data Inputs/Outputs (DQ0~DQ15) Address Input(A0~A20) Lower Byte select Upper Byte select Chip Enable/Select Output Enable Write Enable Sleep enable : When ZZ# is LOW, the CR can be loaded, or the device can enter one of two low-power modes ( DPD or PAR). www.issi.com - SRAM@issi.com IS66WVE2M16BLL Advanced Information 5 ...
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... Vin=VDDQ or 0V, all device pins be static (unswitched) in order to achieve standby current. 6. DPD is enabled when configuration register bit CR[4] is “0”; otherwise, PAR is enabled. Rev.00C | March 2010 CE# WE# OE# UB#/LB www.issi.com - SRAM@issi.com IS66WVE2M16BLL Advanced Information DQ ZZ# Note 4 [15:0] H High-Z 2,5 H Data-Out 1,4 H Data-In 1,3 4,5 L High High High-Z 6 ...
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... Figure 1). During the initialization period, CE# should remain HIGH. When initialization is complete, the device is ready for normal operation. Figure 1: Power-Up Initialization Timing VDD=2.7V VDD VDDQ Rev.00C | March 2010 tPU > 150us Device Initialization www.issi.com - SRAM@issi.com IS66WVE2M16BLL Advanced Information Device ready for normal operation 7 ...
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... WRITE operations, the level of OE “Don’t Care”; WE# overrides OE#. The data to be written is latched on the rising edge of CE#, WE#, or LB#/UB#, whichever occurs first. WE# LOW time must be limited to tCEM. Figure 2. Asynchronous Read Operation Address DQ0- DQ15 CE# UB#/LB# OE# WE# Rev.00C | March 2010 t = READ cycle Time RC VALID ADDRESS VALID DATA www.issi.com - SRAM@issi.com IS66WVE2M16BLL Advanced Information 8 ...
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... Figure 3. Asynchronous WRITE operation Address DQ0- DQ15 CE# UB#/LB# WE# OE# Rev.00C | March 2010 t = WRITE cycle Time WC VALID ADDRESS VALID DATA < t CEM www.issi.com - SRAM@issi.com IS66WVE2M16BLL Advanced Information 9 ...
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... When both the UB#/LB# are disabled (HIGH) during an operation, the device prevents the data bus from receiving or transmitting data. Although the device may appear to be deselected, it remains in active mode as long as CE# remains LOW. Rev.00C | March 2010 ADD0 ADD1 ADD2 APA APA D0 D1 www.issi.com - SRAM@issi.com IS66WVE2M16BLL Advanced Information ADD3 t APA ...
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... The setting selected must be for a temperature higher than the case temperature of the device. If the case temperature is +50°C, the system can minimize self refresh current consumption by selecting the +70°C setting. The +15°C and +45°C settings would result in inadequate refreshing and cause data corruption. Rev.00C | March 2010 www.issi.com - SRAM@issi.com IS66WVE2M16BLL Advanced Information 11 ...
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... Driving ZZ# LOW puts the device in PAR mode if the SLEEP bit in the CR has been set HIGH (CR[4] = 1). The device should not be put into DPD using the CR software-access sequence. Rev.00C | March 2010 www.issi.com - SRAM@issi.com IS66WVE2M16BLL Advanced Information 12 ...
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... Figure 5). The values placed on addresses A[20:0] are latched into the CR on the rising edge of CE# or WE#, whichever occurs first. LB#/UB# are “Don’t Care.” Access using ZZ# is WRITE only. Figure 5: Load Configuration Register Operation Using ZZ# Address CE# WE# t < 500ns ZZ# Rev.00C | March 2010 VALID ADDRESS www.issi.com - SRAM@issi.com IS66WVE2M16BLL Advanced Information 13 ...
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... CR loading. Figure 6 : Configuration Register Write MAX Address ADDRESS DQ0- OUTPUT DQ15 DATA CE# Read UB#/LB# WE# OE# Notes : 0000h Rev.00C | March 2010 MAX MAX ADDRESS ADDRESS OUTPUT *Note1 DATA Read Write www.issi.com - SRAM@issi.com IS66WVE2M16BLL Advanced Information MAX ADDRESS CR VALUE IN Write 14 ...
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... Figure 7 : Configuration Register Read Address MAX ADDRESS DQ0- OUTPUT DQ15 DATA CE# Read UB#/LB# WE# OE# Notes : 0000h Rev.00C | March 2010 MAX MAX ADDRESS ADDRESS OUTPUT *Note1 DATA Read Write www.issi.com - SRAM@issi.com IS66WVE2M16BLL Advanced Information MAX ADDRESS CR VALUE OUT Read 15 ...
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... Rev.00C | March 2010 All Must be set to “0” Page mode disabled (default Page mode enabled +85°C (default +70°C TCR +45° +15° DPD enabled 1 = PAR enabled (default) Must be set to “0” 000 = Full array (default) 1 100 = None of array www.issi.com - SRAM@issi.com IS66WVE2M16BLL Advanced Information Remark 16 ...
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... Setting a lower temperature level would cause data to be corrupted due to insufficient refresh rate. Page Mode READ Operation (CR[7]) Default = Disabled The page mode operation bit determines whether page mode READ operations are enabled In the power-up default state, page mode is disabled. Rev.00C | March 2010 o C Operation www.issi.com - SRAM@issi.com IS66WVE2M16BLL Advanced Information 17 ...
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... VDD VDDQ VIH VIL VOH VOL ILI ILO Symbol IDD1 - OUT IDD1P -70 ISB www.issi.com - SRAM@issi.com IS66WVE2M16BLL Advanced Information Rating -0.5V to 4.0V or VDDQ + 0.3V -0. 4.0V -0. 4.0V -55°Cto + 150°C -40° 85°C + 260°C MIN MAX Unit 2.7 3.6 V 2.7 3.6 V VDDQ-0.4 VDDQ+0 ...
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... Figure 9. Output Load Circuit DUT Rev.00C | March 2010 Conditions Symbol Izz Conditions T =+25°C; C f=1Mhz; VIN=0V ∫∫ Test Points ∫∫ Test Point 50Ω 30pF www.issi.com - SRAM@issi.com IS66WVE2M16BLL Advanced Information TYP MAX Unit Symbol MIN MAX Unit C 2.0 6 3.5 6.5 ...
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... High-Z to Low-Z timings are tested with the circuit shown in Figure 9. The Low-Z timings measure a 100mV transition away from the High-Z (VDDQ/2) level toward either VOH or VOL. 3. Page mode enable only. Rev.00C | March 2010 -70 Min Max www.issi.com - SRAM@issi.com IS66WVE2M16BLL Advanced Information Unit Notes ...
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... High-Z to Low-Z timings are tested with the circuit shown in Figure 9. The Low-Z timings measure a 100mV transition away from the High-Z (VDDQ/2) level toward either VOH or VOL. 3. WE# LOW must be limited to t Rev.00C | March 2010 -70 Min Max (8us) CEM www.issi.com - SRAM@issi.com IS66WVE2M16BLL Advanced Information Unit Notes ...
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... Deep Power-down recovery MIN) Minimum ZZ# pulse width ZZ Table12 . Initialization Timing Requirements Symbol t Initialization Period (required before normal operations) PU Rev.00C | March 2010 -70 Min -70 Min 5 150 10 Parameter www.issi.com - SRAM@issi.com IS66WVE2M16BLL Advanced Information Unit Note Max 500 ns Unit Notes Max -70 Unit Min Max 150 us Notes 22 ...
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... Figure 11: Load Configuration Register Address CE# UB#/LB# WE# OE# t CDZZ ZZ# Figure 12: DPD Entry and Exit Timing t CDZZ ZZ# CE# Rev.00C | March 2010 tPU > 150us Device Initialization t WC OPCODE ZZWE t (MIN) ZZ www.issi.com - SRAM@issi.com IS66WVE2M16BLL Advanced Information VDD(MIN) Device ready for normal operation Device ready for normal operation 23 ...
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... OE# WE# Rev.00C | March 2010 t RC VALID ADDRESS OLZ VALID ADDRESS t PC VALID VALID ADDRESS ADDRESS ADDRESS APA VALID VALID OUTPUT OUTPUT OLZ t OE www.issi.com - SRAM@issi.com IS66WVE2M16BLL Advanced Information VALID OUTPUT BHZ t OHZ VALID VALID ADDRESS VALID VALID OUTPUT OUTPUT BHZ t OHZ 24 ...
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... Figure 15: CE#-Controlled Asynchronous WRITE Address DQ0- DQ15 CE# UB#/LB# OE# WE# Rev.00C | March 2010 t WC VALID ADDRESS WHZ www.issi.com - SRAM@issi.com IS66WVE2M16BLL Advanced Information t WR VALID INPUT CPH 25 ...
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... Figure 16: LB#/UB#-Controlled Asynchronous WRITE Address DQ0- DQ15 t CE UB#/LB# OE# WE# Rev.00C | March 2010 t WC VALID ADDRESS WHZ www.issi.com - SRAM@issi.com IS66WVE2M16BLL Advanced Information t WR VALID INPUT ...
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... Figure 17: WE#-Controlled Asynchronous WRITE Address DQ0- DQ15 CE# UB#/LB# OE# t WPH WE# Rev.00C | March 2010 t WC VALID ADDRESS WHZ www.issi.com - SRAM@issi.com IS66WVE2M16BLL Advanced Information t WR VALID INPUT ...
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... Ordering Information – VDD = 3.0V Industrial Temperature Range: (-40 Config. Speed Order Part No. (ns) 2Mx16 70 IS66WVE2M16BLL-70BLI IS66WVE2M16BLL-70TLI Rev.00C | March 2010 + Package 48-ball TFBGA 48-pin TSOP-I www.issi.com - SRAM@issi.com IS66WVE2M16BLL Advanced Information 28 ...
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... NOTE : 1. Controlling dimension : mm 2. Dimension D1 adn E do not include mold protrusion . 3. Dimension b does not include dambar protrusion/intrusion. 4. Formed leads shall be planar with respect to one another within 0.1mm at the seating plane after final test. Rev.00C | March 2010 www.issi.com - SRAM@issi.com IS66WVE2M16BLL Advanced Information 29 ...
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... Rev.00C | March 2010 www.issi.com - SRAM@issi.com IS66WVE2M16BLL Advanced Information 30 ...