MT45W4MW16BBB-708 WT Micron Technology Inc, MT45W4MW16BBB-708 WT Datasheet
MT45W4MW16BBB-708 WT
Specifications of MT45W4MW16BBB-708 WT
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MT45W4MW16BBB-708 WT Summary of contents
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Async/Page/Burst CellularRAM MT45W4MW16B* *Note: Not recommended for new designs. For the latest data sheet, refer to Micron’s Web site: Features • Single device supports asynchronous, page, and burst operations • Random access time: 70ns • voltages ...
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Table of Contents General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: Ball Assignment – 54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1: VFBGA Ball Descriptions ...
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General Description Micron for low-power, portable applications. The MT45W4MW16BFB is a 64Mb DRAM core device organized as 4 Meg x 16 bits. This device includes an industry-standard burst mode Flash interface that dramatically increases read/write bandwidth compared with other low-power ...
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Table 1: VFBGA Ball Descriptions VFBGA Assignment Symbol Type E3, H6, G2, H1, A[21:0] Input D3, E4, F4, F3, G4, G3, H5, H4, H3, H2, D4, C4, C3, B4, B3, A5, A4 CLK Input J3 ADV# Input A6 ...
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Bus Operations Table 2: Bus Operations – Asynchronous Mode Mode Power Read Active Write Active Standby Standby Idle No Operation Active Configuration Register DPD Deep Power-Down Table 3: Bus Operations – Burst Mode Mode Power Async Read Active Async Write ...
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Part-Numbering Information Micron CellularRAM devices are available in several different configurations and densi- ties (see Figure 3). Figure 3: Part Number Chart Micron Technology Product Family 45 = PSRAM/CellularRAM Memory Operating Core Voltage W ...
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Functional Description In general, the MT45W4MW16BFB device is a high-density alternative to SRAM and Pseudo SRAM products, popular in low-power, portable applications. The MT45W4MW16BFB device contains a 67,108,864-bit DRAM core, organized as 4,194,304 addresses by 16 bits. The device implements ...
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Figure 5: READ Operation (ADV = LOW) CE# OE# WE# ADDRESS DATA LB#/UB# Note: ADV must remain LOW for page mode operation. Figure 6: WRITE Operation (ADV = LOW) CE# OE# WE# ADDRESS DATA LB#/UB# Page Mode READ Operation Page ...
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The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer t than Figure 7: Page Mode READ Operation (ADV = LOW) CE# OE# WE# ADDRESS DATA LB#/UB# Burst Mode Operation Burst mode operations enable high-speed ...
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Figure 8: Burst Mode READ (4-word Burst) CLK ADDRESS A[21:0] ADV# CE# OE# WE# WAIT DQ[15:0] LB#/UB# READ Burst Identified Note: Non-default BCR settings for burst mode READ (4-word burst): Latency code two (three clocks); WAIT active LOW; WAIT asserted ...
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Mixed-Mode Operation The device can support a combination of synchronous READ and asynchronous WRITE operations when the BCR is configured for synchronous operation. The asynchronous READ and WRITE operations require that the clock (CLK) remain static (HIGH or LOW) during ...
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LB#/UB# Operation The LB# enable and UB# enable signals support byte-wide data transfers. During READ operations, the enabled byte(s) are driven onto the DQs. The DQs associated with a dis- abled byte are put into a High-Z state during a ...
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Figure 12: Refresh Collision During WRITE Operation V IH CLK VALID A[21:0] ADDRESS ADV ...
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Low-Power Operation Standby Mode Operation During standby, the device current consumption is reduced to the level necessary to per- form the DRAM refresh operation. Standby operation occurs when CE# is HIGH. The device will enter a reduced power state upon ...
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Configuration Registers Two user-accessible configuration registers define the device operation. The bus config- uration register (BCR) defines how the CellularRAM interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh ...
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Figure 14: Configuration Register WRITE in Synchronous Mode Followed by READ ARRAY Operation CLK Latch Control Register Value A[21:0] OPCODE (except A19 A19 t SP CRE ADV CSP ...
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Software Access Software access of the configuration registers uses a sequence of asynchronous READ and asynchronous WRITE operations. The contents of the configuration registers can be read or modified using the software sequence. The configuration registers are loaded using a ...
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Figure 16: Read Configuration Register ADDRESS CE# OE# WE# LB#/UB# DATA Notes: 1. The WRITE on the third cycle must be CE#-controlled. 2. CE# must be HIGH for 150ns before performing the cycle that reads a configuration regis- ter. PDF: ...
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Bus Configuration Register The BCR defines how the CellularRAM device interacts with the system memory bus. Page mode operation is enabled by a bit contained in the RCR. Figure 17 describes the control bits in the BCR. At power-up, the ...
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Table 4: Sequence and Burst Length 4-Word Burst Wrap Starting Burst Address Length BCR[3] Wrap (Decimal) Linear 0 0-1-2-3 1 1-2-3-0 2 2-3-0-1 3 3-0-1 Yes 6 7 ... 0-1-2-3 1 1-2-3-4 2 2-3-4-5 ...
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Output Impedance (BCR[5]) Default = Outputs Use Full Drive Strength The output driver strength can be altered to adjust for different data bus loading scenar- ios. The reduced-strength option will be more than adequate in stacked chip (Flash + CellularRAM) ...
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Figure 20: WAIT Configuration During Burst Operation CLK WAIT WAIT DQ[15:0] Note: Non-default BCR setting for WAIT configuration during burst operation: WAIT active LOW. WAIT Polarity (BCR[10]) Default = WAIT Active HIGH The WAIT polarity bit indicates whether an asserted ...
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Operating Mode (BCR[15]) Default = Asynchronous Operation The operating mode bit selects either synchronous burst operation or the default asyn- chronous mode of operation. PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst ...
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Refresh Configuration Register The refresh configuration register (RCR) defines how the CellularRAM device performs its transparent self refresh. Altering the refresh parameters can dramatically reduce cur- rent consumption during standby mode. Page mode control is also embedded into the RCR. ...
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Partial-Array Refresh (RCR[2:0]) Default = Full Array Refresh The PAR bits restrict refresh operation to a portion of the total memory array. This fea- ture allows the device to reduce standby current by refreshing only that part of the mem- ...
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Electrical Characteristics Table 7: Absolute Maximum Ratings Parameter Voltage to Any Ball Except Voltage on V Supply Relative Voltage Supply Relative Storage Temperature (plastic) Operating Temperature ...
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Table 8: Electrical Characteristics and Operating Conditions Wireless Temperature Description Supply Voltage I/O Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Operating Current Asynchronous Random READ/ WRITE Asynchronous ...
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Maximum and Typical Standby Currents The following tables and figures refer to the maximum and typical standby currents for the MT45W4MW16BFB device. The typical values shown in Figure 23 on page 31 are measured with the appropriate PAR and TCR ...
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Figure 23: Typical Refresh Current vs. Temperature ( -30 -20 -10 0 Note: Typical I Table 11: Deep Power-Down Specifications Description Deep Power-Down PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 ...
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Table 12: Capacitance Description Input Capacitance Input/Output Capacitance (DQ) Notes: 1. These parameters are verified in device characterization and are not 100 percent tested. Figure 24: AC Input/Output Reference Waveform Input V SS Notes test ...
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Table 14: Asynchronous READ Cycle Timing Requirements 1 Parameter Address Access Time ADV# Access Time Page Access Time Address Hold from ADV# HIGH Address Setup to ADV# HIGH LB#/UB# Access Time LB#/UB# Disable to DQ High-Z Output LB#/UB# Enable to ...
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Table 15: Burst READ Cycle Timing Requirements 1 Parameter Burst to READ Access Time CLK to Output Delay Burst OE# LOW to Output Delay CE# HIGH between Subsequent Mixed-Mode Operations Maximum CE# Pulse Width CE# LOW to WAIT Valid CLK ...
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Table 16: Asynchronous WRITE Cycle Timing Requirements Parameter Address and ADV# LOW Setup Time Address Hold from ADV# Going HIGH Address Setup to ADV# Going HIGH Address Valid to End of WRITE LB#/UB# Select to End of WRITE CE# LOW ...
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Table 17: Burst WRITE Cycle Timing Requirements Parameter CE# HIGH between Subsequent Mixed-Mode Operations Minimum CE# Pulse Width CE# LOW to WAIT Valid Clock Period CE# Setup to CLK Active Edge Hold Time from Active CLK Edge Chip Disable to ...
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Timing Diagrams Figure 26: Initialization Period Vcc, VccQ = 1.70V Table 18: Initialization Timing Parameters Parameter Initialization Period (required before normal operations) PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 ...
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Figure 27: Asynchronous READ A[21:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] WAIT Table 19: Asynchronous READ Timing Parameters -70x Symbol Min Max Min BHZ 8 t BLZ 10 t CEW 1 7.5 t ...
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Figure 28: Asynchronous READ Using ADV# A[21:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] WAIT Table 20: Asynchronous READ Timing Parameters Using ADV# -70x Symbol Min Max Min AADV t 5 AVH t AVS 10 t ...
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Figure 29: Page Mode READ A[21:4] A[3:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] WAIT Table 21: Asynchronous READ Timing Parameters – Page Mode Operation -70x Symbol Min Max Min APA ...
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Figure 30: Single-Access Burst READ Operation V IH CLK A[21:0] VALID ADDRESS ADV CSP ...
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Figure 31: 4-Word Burst READ Operation V IH CLK VALID A[21:0] ADDRESS ADV CSP ...
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Figure 32: 4-Word Burst READ Operation (with LB#/UB CLK VALID A[21:0] ADDRESS ADV CSP ...
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Figure 33: READ Burst Suspend V IH CLK VALID A[21:0] V ADDRESS ADV CSP OE# ...
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Figure 34: Continuous Burst READ Showing an Output Delay with BCR[ for End-of-Row Condition V IH CLK CLK V IH A[21: ADV LB#/UB ...
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Figure 35: CE#-Controlled Asynchronous WRITE A[21:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] IN DQ[15:0] OUT WAIT Table 27: Asynchronous WRITE Timing Parameters – CE#-Controlled -70x Symbol Min Max Min CEW ...
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Figure 36: LB#/UB#-Controlled Asynchronous WRITE A[21:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] IN DQ[15:0] OUT WAIT Table 28: Asynchronous WRITE Timing Parameters – LB#/UB#-Controlled -70x Symbol Min Max Min ...
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Figure 37: WE#-Controlled Asynchronous WRITE A[21:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] IN DQ[15:0] OUT WAIT Table 29: Asynchronous WRITE Timing Parameters – WE#-Controlled -70x Symbol Min Max Min CEW ...
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Figure 38: Asynchronous WRITE Using ADV# A[21:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] IN DQ[15:0] OUT WAIT Table 30: Asynchronous WRITE Timing Parameters Using ADV# -70x Symbol Min Max Min AVH t AVS 10 t ...
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Figure 39: Burst WRITE Operation V IH CLK A[21:0] VALID ADDRESS ADV LB#/UB CSP V IH CE# ...
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Figure 40: Continuous Burst WRITE Showing an Output Delay with BCR[ for End-of-Row Condition V IH CLK CLK V IH A[21: ADV LB#/UB ...
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Figure 41: Burst WRITE Followed by Burst READ t CLK V IH CLK A[21:0] VALID V ADDRESS ADV LB#/UB ...
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Figure 42: Asynchronous WRITE Followed by Burst READ V IH CLK A[21:0] VALID ADDRESS AVS t AVH t VPH V IH ADV CVS LB#/UB# ...
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Figure 43: Asynchronous WRITE Followed By Burst READ – ADV# LOW V IH CLK A[21:0] VALID ADDRESS VALID ADDRESS ADV LB#/UB# V ...
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Figure 44: Burst READ Followed by Asynchronous WRITE (WE#-Controlled CLK A[21:0] VALID ADDRESS ADV CSP V IH CE# V ...
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Figure 45: Burst READ Followed by Asynchronous WRITE Using ADV CLK A[21:0] VALID ADDRESS ADV CSP V IH CE# ...
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Figure 46: Asynchronous WRITE Followed by Asynchronous READ – ADV# LOW V IH A[21:0] VALID ADDRESS ADV LB#/ ...
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Figure 47: Asynchronous WRITE Followed by Asynchronous READ V IH A[21:0] VALID ADDRESS AVS t VPH ADV CVS V IH LB#/UB CE ...
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Figure 48: 54-Ball VFBGA SEATING PLANE C 0.10 C 54X Ø0.37 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS Ø0.35. BALL A6 6.00 3.00 1.875 Notes: 1. All dimensions in millimeters; MAX/MIN, or typical, as noted. ...
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Revision History Rev ...
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Updated I • Added ADV# timing parameters and • Clarified CE# LOW time limited by refresh—must not stay LOW longer than • Aligned • Added Operation descriptions and timing diagrams. • Deleted Appendix A (extended timings and all references). ...