MT45W4MW16BBB-708 WT Micron Technology Inc, MT45W4MW16BBB-708 WT Datasheet - Page 21

• Manufacturer Part Number: MT45W4MW16BBB-708 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45W4MW16BBB-708 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Bus Configuration Register
Figure 17:
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
All must be set to "0"
Bus Configuration Register Definition
Reserved
BCR[19]
A[21:20]
21–20
0
1
BCR[15]
Register
Select
0
1
Select RCR
Select BCR
19
A19
Note:
BCR[13]
Must be set to "0"
0
0
0
0
1
1
1
1
Reserved
A[18:16]
18–16
Asynchronous access mode (default)
Synchronous burst access mode
BCR[10]
BCR[12] BCR[11]
The BCR defines how the CellularRAM device interacts with the system memory bus.
Page mode operation is enabled by a bit contained in the RCR. Figure 17 describes the
control bits in the BCR. At power-up, the BCR is set to 9D4Fh.
The BCR is accessed using CRE and A[19] HIGH, or through the configuration register
software sequence with DQ = 0001h on the third cycle.
Register Select
0
1
0
0
1
1
0
0
1
1
Operating
BCR[8]
Mode
Operation Mode
All burst WRITEs are continuous.
0
1
15
A15
Active LOW
Active HIGH (default)
0
1
0
1
0
1
0
1
Must be set to "0"
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Reserved
Asserted one data cycle before delay (default)
Asserted during delay
Code 0–Reserved
Code 1–Reserved
Code 2
Code 3 (Default)
Code 4–Reserved
Code 5–Reserved
Code 6–Reserved
Code 7–Reserved
14
Latency Counter
A14
WAIT Polarity
A13
13 12 11
Counter
Latency
WAIT Configuration
A12A11 A10
Polarity
WAIT
10
Must be set to "0"
Reserved
9
A9
21
Configuration (WC)
WAIT
8
A8
BCR[6]
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0
1
Must be set to "0"
Reserved
BCR[5]
Not supported
Rising edge (default)
A7
7
0
1
BCR[3]
Configuration (CC)
1/4 Drive
0
1
Full Drive (default)
Clock Configuration
Output Impedance
Clock
BCR[2]
6
A6
0
0
0
1
Burst wraps within the burst length
Burst no wrap (default)
BCR[1] BCR[0]
Configuration Registers
0
1
1
1
Impedance
Output
Burst Wrap (Note 1)
5
A5
1
0
1
1
Must be set to "0"
©2003 Micron Technology, Inc. All rights reserved.
Reserved
4 words
8 words
16 words
Continuous burst (default)
A4
4
Burst Length (Note 1)
Wrap (BW)*
Burst
3
A3
Length (BL)*
2
A2 A1 A0
Burst
1
0