MT45V512KW16PEGA-70 WT Micron Technology Inc, MT45V512KW16PEGA-70 WT Datasheet - Page 11

• Manufacturer Part Number: MT45V512KW16PEGA-70 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45V512KW16PEGA-70 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Page Mode READ Operation
Figure 7:
LB#/UB# Operation
PDF: 09005aef82f264f6/Source: 09005aef82f264aa
8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. C 4/08 EN
Page Mode READ Operation (ADV = LOW)
Page mode is a performance-enhancing extension to the legacy asynchronous READ
operation. In page-mode-capable products, an initial asynchronous read access is
performed, then adjacent addresses can be read quickly by simply changing the low-
order address. Addresses A[3:0] are used to determine the members of the 16-address
PSRAM page. Any change in addresses A[4] or higher will initiate a new
Figure 7).
Page mode takes advantage of the fact that adjacent addresses can be read faster than
random addresses. WRITE operations do not include comparable page mode function-
ality.
The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer
than
LB#/UB#
The lower byte (LB#) and upper byte (UB#) enable signals accommodate byte-wide data
transfers. During READ operations, enabled bytes are driven onto the DQ. The DQ
signals associated with a disabled byte are put into a High-Z state during a READ opera-
tion. During WRITE operations, disabled bytes are not transferred to the memory array,
and the internal value remains unchanged. During a WRITE cycle, the data to be written
is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first.
When both the LB# and UB# are disabled (HIGH) during an operation, the device
prevents the data bus from receiving or transmitting data. Although the device may
appear to be deselected, it remains in active mode as long as CE# remains LOW.
Address
Data
WE#
OE#
CE#
CE#
t
CEM.
8Mb: 3.0V Core Async/Page PSRAM Memory 512K x 16
Address[0]
t AA
D[0]
11
t APA
Address
[1]
< t CEM
D[1]
t APA
Address
[2]
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D[2]
t APA
Address
[3]
D[3]
Don't Care
Bus Operating Modes
©2007 Micron Technology, Inc. All rights reserved.
t
AA access (see