AT88SA10HS-SH-T Atmel, AT88SA10HS-SH-T Datasheet - Page 6
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AT88SA10HS-SH-T
Manufacturer Part Number
AT88SA10HS-SH-T
Description
Processors - Application Specialized 58951-Eb CryptoAuth SHA-256 HST IC GRN
Manufacturer
Atmel
Datasheet
1.AT88SA10HS-SH-T.pdf
(23 pages)
Specifications of AT88SA10HS-SH-T
Lead Free Status / RoHS Status
Supplier Unconfirmed
6
Table 3-1.
Table 3-2.
Atmel AT88SA10HS Host Authentication Chip
Parameter
Wake Low
Duration
Wake Delay to
Data Comm.
Start pulse
duration
Zero
transmission
high pulse
Zero
transmission
low pulse
Bit time
Turn around
delay
High side
glitch filter @
active
Low side glitch
filter @ active
Low side glitch
filter @ sleep
IO Timeout
Parameter
Watchdog
reset
Pause Length
‡
AC Parameters
AC Parameters continued
Symbol
t
t
t
t
t
t
t
t
t
t
t
Symbol
t
t
WLO
WHI
START
ZHI
ZLO
BIT
TURNAROUND
HIGNORE_A
LIGNORE_A
LIGNORE_S
TIMEOUT
WATCHDOG
PAUSE
Direction
To Atmel
AT88SA10HS
To Atmel
AT88SA10HS
To Atmel
AT88SA10HS
From Atmel
AT88SA10HS
To Atmel
AT88SA10HS
From Atmel
AT88SA10HS
To Atmel
AT88SA10HS
From Atmel
AT88SA10HS
To Atmel
AT88SA10HS
From Atmel
AT88SA10HS
From Atmel
AT88SA10HS
To Atmel
AT88SA10HS
To Atmel
AT88SA10HS
To Atmel
AT88SA10HS
To Atmel
AT88SA10HS
To Atmel
AT88SA10HS
Direction
To Atmel
AT88SA10HS
-
15µs
Min
Min
2.5
4.1
4.6
4.1
4.6
4.1
4.6
60
37
41
28
45
45
45
18
2
3
4.34
4.34
4.34
Typ
Typ
6.0
6.0
6.0
39
54
60
65
25
4
46ms
4.56
4.56
4.56
Max
Max
8.6
8.6
8.6
5.7
45
78
95
85
32
-
-
Unit Notes
Unit Notes
ms Signal should be stable high for this entire
ms Refer to Section 4.4.1
ms Duration during which the chip will ignore IO
µs Signal can be stable in either high or low
µs
µs
µs
µs
µs
µs
µs If the bit time exceeds t
µs
µs Atmel AT88SA10HS will initiate the first low
µs Pulses shorter than this in width will be
ns Pulses shorter than this in width will be
ns Pulses shorter than this in width will be
s
levels during extended sleep intervals
duration. t
chip will transition to sleep
AT88SA10HS will enter sleep mode and the
Wake token must be resent
going transition after this time interval
following the end of the Transmit flag
After Atmel AT88SA10HS transmits the last
bit of a block, system must wait this interval
before sending the first bit of a flag
ignored by the chip, regardless of its state
when active
ignored by the chip, regardless of its state
when active
ignored by the chip when in sleep mode
Max. time from Wake until chip is forced into
sleep mode. See Section 4.5
on the bus. See PauseShort command,
Section 5.7
WHI
must not exceed t
TIMEOUT
then Atmel
TIMEOUT
8595F–SMEM–8/10
or the