NAND32GAH0HZA5E Micron Technology Inc, NAND32GAH0HZA5E Datasheet - Page 16

• Manufacturer Part Number: NAND32GAH0HZA5E
• Manufacturer: Micron Technology Inc

Specifications of NAND32GAH0HZA5E

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

High speed MultiMediaCard operation
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6.1
6.2
6.3
6.4
6.5
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High speed MultiMediaCard operation
All communication between the host and the device is controlled by the host (master).
The following section provides an overview of the identification and data transfer modes,
commands, dependencies, various operation modes and restrictions for controlling the clock
signal. For detailed information, refer to section 7 of the JEDEC Standard Specification No.
JESD84-A43.
Boot mode
The host can read boot data from NANDxxxAH0H by keeping CMD line Low after power-on
or sending CMD0 with argument + 0xFFFFFFFA (optional for slave), before issuing CMD1.
The data can be read from either boot area or user area depending on the register setting.
Refer to section 7.2 of the JEDEC Standard Specification No. JESD84-A43.
Identification mode
When in card identification mode, the host resets the NANDxxxAH0H, validates the
operating voltage range and the access mode, identifies the device and assigns a relative
address (RCA) to it. For more information see section 7.3 of the JEDEC Standard
Specification No. JESD84-A43.
Data transfer mode
The device enters data transfer mode once an RCA is assigned to it. When the device is in
standby mode, issuing the CMD7 command along with the RCA, selects the device and puts
it into the transfer state. The host enters data transfer mode after identifying the
NANDxxxAH0H on the bus. When the device is in standby state, communication over the
CMD and DAT lines is in push-pull mode.
The section 7.5 of the JEDEC Standard Specification No. JESD84-A43 contains more
detailed information about data read and write, erase, write protect management,
lock/unlock operations, the switch function command, high speed mode selection, and bus
testing procedure. Moreover section 7.5.7 contains a detailed description of the reliable
write features supported by the NANDxxxAH0H.
Clock control
Refer to section 7.6 of the JEDEC Standard Specification No. JESD84-A43.
Error conditions
Refer to section 7.7 of the JEDEC Standard Specification No. JESD84-A43.
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