MR2A16ATS35CR Freescale, MR2A16ATS35CR Datasheet - Page 12
![no-image](/images/manufacturer_photos/0/2/261/freescale_sml.jpg)
MR2A16ATS35CR
Manufacturer Part Number
MR2A16ATS35CR
Description
Manufacturer
Freescale
Datasheet
1.MR2A16ATS35CR.pdf
(22 pages)
Specifications of MR2A16ATS35CR
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Package Type
TSOP-II
Mounting
Surface Mount
Pin Count
44
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Compliant
Timing Specifications
12
Write cycle time
Address set-up time
Address valid to end of write (G high)
Address valid to end of write (G low)
Enable to end of write (G high)
Enable to end of write (G low)
Data valid to end of write
Data hold time
Write recovery time
NOTES:
1
2
3
4
5
6
7
8
A write occurs during the overlap of E low and W low.
Due to product sensitivities to noise, power supplies must be properly grounded and decoupled
and bus contention conditions must be minimized or eliminated during read and write cycles.
If G goes low at the same time or after W goes low, the output will remain in a high-impedance
state.
After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a
minimum of 2 ns.
The minimum time between E being asserted low in one cycle to E being asserted low in a
subsequent cycle is the same as the minimum cycle time allowed for the device.
All write cycle timings are referenced from the last valid address to the first transition address.
If E goes low at the same time or after W goes low, the output will remain in a high-impedance state.
If E goes high at the same time or before W goes high, the output will remain in a high-impedance
state.
6
Table 11. Write Cycle Timing 2 (E Controlled)
Parameter
7, 8
MR2A16A Data Sheet, Rev. 6
Symbol
t
t
t
t
t
t
t
t
t
t
t
ELWH
ELWH
AVEH
AVEH
DVEH
EHDX
EHAX
ELEH
ELEH
AVAV
AVEL
Min
1, 2, 3, 4, 5
35
18
20
15
15
10
12
0
0
Max
—
—
—
—
—
—
—
—
—
Freescale Semiconductor
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns