MR2A16ATS35CR Freescale, MR2A16ATS35CR Datasheet - Page 14

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MR2A16ATS35CR

Manufacturer Part Number
MR2A16ATS35CR
Description
Manufacturer
Freescale
Datasheet

Specifications of MR2A16ATS35CR

Operating Temperature (max)
70C
Operating Temperature (min)
0C
Package Type
TSOP-II
Mounting
Surface Mount
Pin Count
44
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Compliant
Timing Specifications
14
NOTES:
Write cycle time
Address set-up time
Address valid to end of write (G high)
Address valid to end of write (G low)
Byte pulse width (G high)
Byte pulse width (G low)
Data valid to end of write
Data hold time
Write recovery time
1
2
3
4
5
6
7
A write occurs during the overlap of E low and W low.
Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and
bus contention conditions must be minimized or eliminated during read and write cycles.
If G goes low at the same time or after W goes low, the output will remain in a high-impedance state.
After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a minimum
of 2 ns.
If both byte control signals are asserted, the two signals must have no more than 2 ns skew between
them.
The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent
cycle is the same as the minimum cycle time allowed for the device.
All write cycle timings are referenced from the last valid address to the first transition address.
Table 12. Write Cycle Timing 3 (LB/UB Controlled)
7
Parameter
MR2A16A Data Sheet, Rev. 6
Symbol
t
t
t
t
t
t
t
t
t
t
t
BLWH
BLWH
DVBH
BHDX
AVBH
AVBH
BHAX
AVAV
AVBL
BLEH
BLEH
Min
35
18
20
15
15
10
12
0
0
1, 2, 3, 4, 5, 6
Max
Freescale Semiconductor
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns

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