AT24C128SX-09DT Atmel, AT24C128SX-09DT Datasheet - Page 9

• Manufacturer Part Number: AT24C128SX-09DT
• Manufacturer: Atmel

Specifications of AT24C128SX-09DT

• Lead Free Status / RoHS Status: Compliant

Figure 10. Page Write
Note:
Read Operations
1661B–SEEPR–04/04
1. * = DON’T CARE bit
2. † = DON’T CARE bit for the 128K
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-
ing a start condition followed by the device address word. The read/write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a zero, allowing the read or write sequence to continue.
Read operations are initiated the same way as write operations with the exception that
the read/write select bit in the device address word is set to one. There are three read
operations: current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the
last address accessed during the last read or write operation, incremented by one. This
address stays valid between operations as long as the chip power is maintained. The
address “roll over” during read is from the last byte of the last memory page, to the first
byte of the first page.
Once the device address with the read/write select bit set to one is clocked in and
acknowledged by the EEPROM, the current address data word is serially clocked out.
The microcontroller does not respond with an input zero but does generate a following
stop condition (refer to Figure 11).
Figure 11. Current Address Read
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the
data word address. Once the device address word and data word address are clocked
in and acknowledged by the EEPROM, the microcontroller must generate another start
condition. The microcontroller now initiates a current address read by sending a device
address with the read/write select bit high. The EEPROM acknowledges the device
SDA LINE
S
T
A
R
T
M
S
B
ADDRESS
DEVICE
AT24C128SC/AT24C256SC
L
S
B
R
/
W
R
E
A
D
A
C
K
DATA
N
O
A
C
K
S
T
O
P
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