MT8VDDT6464AG-265DB Micron Technology Inc, MT8VDDT6464AG-265DB Datasheet - Page 13
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MT8VDDT6464AG-265DB
Manufacturer Part Number
MT8VDDT6464AG-265DB
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT8VDDT6464AG-265DB.pdf
(15 pages)
Specifications of MT8VDDT6464AG-265DB
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
184UDIMM
Device Core Size
64b
Organization
64Mx64
Total Density
512MByte
Chip Density
512Mb
Maximum Clock Rate
266MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
1.16A
Number Of Elements
8
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
184
Mounting
Socket
Lead Free Status / RoHS Status
Not Compliant
Serial Presence-Detect
Table 12:
Table 13:
Serial Presence-Detect Data
PDF: 09005aef80867ab3/Source: 09005aef80867a99
DD8C32_64x64A.fm - Rev. J 8/08 EN
Parameter/Condition
Supply voltage
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Output low voltage: I
Input leakage current: V
Output leakage current: V
Standby current: SCL = SDA = V
Power supply current: SCL clock frequency = 100 kHz
Parameter/Condition
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
Clock/data fall time
Clock/data rise time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
Serial Presence-Detect EEPROM DC Operating Conditions
Serial Presence-Detect EEPROM AC Operating Conditions
Notes:
OUT
IN
= 3mA
OUT
= GND to V
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
For the latest serial presence-detect data, refer to Micron's SPD page:
www.micron.com/SPD.
= GND to V
DD
the falling or rising edge of SDA.
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-
tance, and the EEPROM does not respond to its slave address.
- 0.3V; All other inputs = V
DD
DD
256MB, 512MB (x64, SR) 184-Pin DDR SDRAM UDIMM
13
SS
or V
DD
t
WRC) is the time from a valid stop condition of a write
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
Symbol
Symbol
t
t
t
t
HD:DAT
V
HD:STA
SU:DAT
SU:STO
SU:STA
t
t
t
t
HIGH
DDSPD
LOW
f
WRC
t
t
V
BUF
V
V
I
I
SCL
I
AA
DH
I
t
LO
CC
t
SB
t
OL
LI
F
R
IH
IL
I
V
DDSPD
Min
200
100
0.2
1.3
0.6
0.6
1.3
0.6
0.6
0
–
–
–
–
–
Min
–1.0
2.3
–
–
–
–
–
Serial Presence-Detect
× 0.7 V
©2003 Micron Technology, Inc. All rights reserved.
Max
300
300
400
0.9
50
10
–
–
–
–
–
–
–
–
–
V
DDSPD
DDSPD
Max
3.6
0.4
2.0
10
10
30
Units
kHz
+ 0.5
× 0.3
ms
µs
µs
ns
ns
ns
µs
µs
µs
ns
µs
ns
µs
µs
Notes
Units
mA
µA
µA
µA
V
V
V
V
1
2
2
3
4