CY14E064L-SZ25XI Cypress Semiconductor Corp, CY14E064L-SZ25XI Datasheet - Page 4

• Manufacturer Part Number: CY14E064L-SZ25XI
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of CY14E064L-SZ25XI

• Word Size: 8b
• Organization: 8Kx8
• Density: 64Kb
• Interface Type: Parallel
• Access Time (max): 25ns
• Operating Supply Voltage (typ): 5V
• Package Type: SOIC
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: -40C to 85C
• Pin Count: 28
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Document Number: 001-06543 Rev. *E
In system power mode, both V
the +5V power supply without the 68 μF capacitor. In this
mode, the AutoStore function of the CY14E064L operates on
the stored system charge as power goes down. The user
must, however, guarantee that V
during the 10 ms STORE cycle.
If an automatic STORE on power loss is not required, then V
is tied to ground and + 5V is applied to V
is the AutoStore Inhibit mode, where the AutoStore function is
disabled. If the CY14E064L is operated in this configuration,
references to V
sheet. In this mode, STORE operations are triggered through
software control or the HSB pin. It is not permissible to change
between these three options at will. To reduce unnecessary
Figure 2. AutoStore Inhibit Mode
nonvolatile stores, AutoStore and Hardware Store operations
are ignored, unless at least one WRITE operation has taken
place since the most recent STORE or RECALL cycle.
Software initiated STORE cycles are performed regardless of
whether a WRITE operation has taken place. The HSB signal
is monitored by the system to detect if an AutoStore cycle is in
progress.
Hardware STORE (HSB) Operation
The CY14E064L provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin is used
to request a hardware STORE cycle. When the HSB pin is
driven LOW, the CY14E064L conditionally initiates a STORE
operation after t
WRITE to the SRAM takes place since the last STORE or
RECALL cycle. The HSB pin also acts as an open drain driver
that is internally driven LOW to indicate a busy condition, while
the STORE (initiated by any means) is in progress.
SRAM READ and WRITE operations, that are in progress
when HSB is driven LOW by any means, are given time to
complete before the STORE operation is initiated. After HSB
goes LOW, the CY14E064L continues SRAM operations for
t
DELAY
. During t
CC
DELAY
DELAY
14
1
are changed to V
. An actual STORE cycle only begins if a
, multiple SRAM READ operations take
CC
CC
and V
does not drop below 3.6V
CAP
28
27
26
15
CAP
throughout this data
CAP
are connected to
(Figure
2). This
CC
place. If a WRITE is in progress when HSB is pulled LOW, it
allows a time, t
WRITE cycles requested after HSB goes LOW are inhibited
until HSB returns HIGH.
The HSB pin is used to synchronize multiple CY14E064L while
using a single larger capacitor. To operate in this mode, the
HSB pin is connected together to the HSB pins from the other
CY14E064L. An external pull up resistor to +5V is required,
since HSB acts as an open drain pull down. The V
from the other CY14E064L parts are tied together and share
a single capacitor. The capacitor size is scaled by the number
of devices connected to it. When any one of the CY14E064L
detects a power loss and asserts HSB, the common HSB pin
causes all parts to request a STORE cycle. (A STORE takes
place in those CY14E064L that are written since the last
nonvolatile cycle.)
During any STORE operation, regardless of how it is initiated,
the CY14E064L continues to drive the HSB pin LOW,
releasing it only when the STORE is complete. After
completing the STORE operation, the CY14E064L remains
disabled until the HSB pin returns HIGH.
If HSB is not used, it is left unconnected.
Hardware RECALL (Power Up)
During power up or after any low power condition (V
V
once again exceeds the sense voltage of V
cycle is automatically initiated and takes t
If the CY14E064L is in a WRITE state at the end of power up
RECALL, the SRAM data is corrupted. To help avoid this
situation, a 10 Kohm resistor is connected either between WE
and system V
Software STORE
Using a software address sequence, transfer the data from the
SRAM to the nonvolatile memory. The CY14E064L software
STORE cycle is initiated by executing sequential CE controlled
READ cycles from six specific address locations in exact
order. During the STORE cycle, an erase of the previous
nonvolatile data is first performed followed by a program of the
nonvolatile elements. When a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is
used for STORE initiation, it is important that no other READ
or WRITE accesses intervene in the sequence. If they
intervene, the sequence is aborted and no STORE or RECALL
takes place.
To initiate the software STORE cycle, the following READ
sequence is performed:
The software sequence is clocked with CE controlled READs
or OE controlled READs. When the sixth address in the
sequence is entered, the STORE cycle commences and the
chip is disabled. It is important that READ cycles and not
1. Read address 0x0000, Valid READ
2. Read address 0x1555, Valid READ
3. Read address 0x0AAA, Valid READ
4. Read address 0x1FFF, Valid READ
5. Read address 0x10F0, Valid READ
6. Read address 0x0F0F, Initiate STORE cycle
SWITCH
), an internal RECALL request is latched. When V
CC
or between CE and system V
DELAY
to complete. However, any SRAM
HRECALL
SWITCH
CY14E064L
CC
.
to complete.
, a RECALL
Page 4 of 17
CAP
CC
pins
CC
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