HSP43216VC-52 Intersil, HSP43216VC-52 Datasheet - Page 13

• Manufacturer Part Number: HSP43216VC-52
• Manufacturer: Intersil

Specifications of HSP43216VC-52

• Lead Free Status / RoHS Status: Not Compliant

AIN0-15
If external multiplexing is selected (INT/EXT = 0), a
demultiplex function is required off chip to break the input data
stream into even and odd samples for input through AIN0-15
and BIN0-15. In this mode, the real and imaginary processing
legs run at the input clock rate which allows the device to
perform the down convert and decimate function on real
signals sampled at up to twice the maximum speed grade of
the device (104 MSPS). With external multiplexing, the
minimum pipeline delay through the upper processing leg is 9
CLK’s and the pipeline delay through the lower processing leg
is 26 CLK’s as shown in Figure 15B. To synchronize the even
samples input through AIN0-15 with the zero degree cosine
term of the quadrature LO, SYNC should be asserted on the
same clock that the target sample is present at the input of the
part as shown in Figure 17. NOTE: For proper operation,
the samples demultiplexed to the AIN0-15 input must
precede those input to the BIN0-15 input in sample order.
For example, given a data sequence x0, x1, x2, and x3,
THE SAMPLE DESIGNATED BY THE 0
WITH THE RESPECTIVE COSINE TERMS ON THE UPPER PROCESSING
LEG, AND THE OTHER SAMPLES, THOSE LABELED BY 90
ARE MIXED WITH THE RESPECTIVE SINE TERMS ON THE LOWER LEG.
SYNC
FIGURE 16. DATA SYNCHRONIZATION TO 0
CLK
†
AIN0-15
BIN0-15
Clocked at CLK/2
AIN0-15
QUADRATURE LO
R
E
G
R
E
G
FIGURE 15B. DATA FLOW DIAGRAM FOR DOWN CONVERT AND DECIMATE MODE (INT/EXT = 0)
FIGURE 15A. DATA FLOW DIAGRAM FOR DOWN CONVERT AND DECIMATE MODE (INT/EXT = 1)
R
E
G
R
E
G
R
E
G
0
R
E
G
13
R
E
G
R
E
G
o
1
AND 180
R
G
G
†
E
†
R
E
0
o
2
o
LABELS ARE MIXED
1,-1,1,-1,...
-1,1,-1,1,...
90
-1,1,-1,1,...
1,-1,1,-1,...
o
o
PHASE OF
R
E
G
R
E
G
3
o
180
AND 270
†
R
E
G
†
R
E
G
PIPELINE DELAY 2-35
PIPELINE DELAY 19
o
GROUP DELAY 19
GROUP DELAY 19
†
†
†
†
PIPELINE DELAY 2-35
PIPELINE DELAY 19
EVEN TAP
GROUP DELAY 19
GROUP DELAY 19
ODD TAP
270
HSP43216
o
FILTER
FILTER
,
EVEN TAP
o
ODD TAP
FILTER
FILTER
the demultiplex function would route x0 and x2 to AIN0-
15 and x1 and x3 to BIN0-15.
Quadrature to Real Conversion Mode (MODE1-0 = 11)
The Quadrature to Real Conversion mode is used to
construct a real output from a quadrature input. To
accomplish this, the Halfband Filter Processor interpolates
the quadrature components of the complex input signal by
a factor of two. Next, the Quadrature Up-Convert Processor
spectrally shifts the signal by f
output as described in the f
Processor Section. The direction of the spectral shift is
controlled via the USB/LSB input and is used to designate
the frequency content of the complex input as either the
upper or lower sideband of the resulting real output signal.
A spectral representation of quadrature to real conversion
is shown in Figure 18 for USB/LSB = 1. NOTE: The f
Up-Convert Processor uses quadrature mix factors
FIGURE 17. DATA SYNCHRONIZATION WITH PHASE OF
THE 0
THE SAMPLES INPUT THROUGH AIN0-15 WITH THE COSINE TERM
OF THE QUADRATURE DOWN CONVERT LO.
AIN0-15
SYNC
2
CLK
o
AND 180
2
2
2
DOWN CONVERT LO
R
E
G
R
E
G
o
LABELS INDICATE THE PHASE ALIGNMENT OF
R
G
†
†
E
R
E
G
0
o
R
N
D
R
N
D
0
S
F
M
T
F
M
T
/4 Quadrature Up-Convert
R
N
D
R
N
D
180
S
R
E
G
R
E
G
/4 and derives the real
M
M
F
T
F
T
o
R
E
G
R
E
G
R
E
G
R
E
G
R
E
G
R
E
G
1
0
o
BOUT0-15
AOUT0-15
AOUT0-15
BOUT0-15
OEB
OEA
2
October 6, 2008
180
OEA
OEB
FN3365.10
o
S
/4