ADV7400AKSTZ-80 Analog Devices Inc, ADV7400AKSTZ-80 Datasheet - Page 9

• Manufacturer Part Number: ADV7400AKSTZ-80
• Manufacturer: Analog Devices Inc

Specifications of ADV7400AKSTZ-80

• Lead Free Status / RoHS Status: Compliant

Pin No.
3
4
99
98
81, 19
82, 16
80
78
36
38
37
46
15
64
65
61, 62
68, 69
67
86
85
79
59
35
52
77
Mnemonic
INT
HS/CS
VS
FIELD/DE
SDA1, SDA2
SCLK1, SCLK2
ALSB
RESET
LLC1
XTAL
XTAL1
ELPF
SFL/SYNC_OUT
REFOUT
CML
CAPY1 to CAPY2
CAPC1 to CAPC2
BIAS
HS_IN/CS_IN
VS_IN
DE_IN
NC
DCLK_IN
SOG
SOY
Type
O
O
O
O
I/O
I
I
I
O
I
O
O
O
O
O
I
I
O
I
I
I
NC
I
I
I
Description
Interrupt Pin. This pin can be programmed active low or active high. When SDP/CP
status bits change, this pin triggers an interrupt. The set of events which triggers an
interrupt can be modified via I
Horizontal Synchronization/Composite Synchronization. HS is a horizontal
synchronization output signal in SDP and CP modes. CS is a digital composite
synchronization signal that can be selected while in CP mode.
Vertical Synchronization. Vertical synchronization output signal in SDP and CP
modes.
Field Synchronization/Data Enable. Field synchronization output signal in all
interlaced video modes. This pin also can be enabled as a data enable signal in CP
mode to allow direct connection to a HDMI/DVI Tx IC.
I
SDA2 is the data line for the VBI readback port.
I
control port, and SCLK2 is the clock line for the VBI data readback port.
This pin selects the I
When set to a Logic 0, ALSB sets the address for a write to control port of 0x40 and
the readback address for the VBI port of 0x21. When set to a Logic 1, ALSB sets the
address for a write to the control port of 0x42 and the readback address for the VBI
port of 0x23.
System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required
to reset the ADV7400A circuitry.
Line-locked output clock for the pixel data output by the ADV7400A (the range is
13.5 MHz to 110 MHz for the ADV7400AKSTZ-110; 13.5 MHz to 80 MHz for the
ADV7400AKSTZ-80).
Input pin for 27 MHz crystal, or it can be overdriven by an external 3.3 V 27 MHz clock
oscillator source to clock the ADV7400A.
This pin should be connected to the 27 MHz crystal or left as a no connect if an
external 3.3 V, 27 MHz clock oscillator source is used to clock the ADV7400A. In
crystal mode the crystal must be a fundamental crystal.
The recommend external loop filter must be connected to this ELPF pin.
SFL (Subcarrier Frequency Lock). This pin contains a serial output stream that can be
used to lock the subcarrier frequency when this decoder is connected to any Analog
Devices digital video encoder.
SYNC_OUT is the sliced sync output signal available only in CP mode.
Internal Voltage Reference Output.
Common-Mode Level Pin for the Internal ADCs.
ADC Capacitor Network.
ADC Capacitor Network.
External Bias Setting Pin. Connect the recommended resistor between this pin and
ground.
Can be configured in CP mode to be either a digital HS input signal or a digital CS
input signal, which are used to extract timing in 5-wire or 4-wire RGB mode.
VS Input Signal. Used in CP mode for 5-wire timing mode.
Data Enable Input Signal. Used in 24-bit digital input port mode, for example, 24-bit
RGB data from a DVI Rx IC.
No Connect Pin. This pin can be tied to AGND or AVDD.
Clock Input Signal. Used in 24-bit digital input mode and also in digital CVBS input
mode.
Sync On Green Input Pin. Used in embedded sync mode.
Sync On Luma Input Pin. Used in embedded sync mode.
2
2
C Port Serial Data Input/Output Pin. SDA1 is the data line for the control port and
C Port Serial Clock Input (max clock rate of 400 kHz). SCLK1 is the clock line for the
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2
C address for the ADV7400A control and VBI readback ports.
2
C registers.
ADV7400A